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2016-02-11arches: lib: add main_decl.h for main() declarationAaron Durbin
It is silly to have a single header to declare the main() symbol, however some of the arches provided it while lib/bootblock.c relied on the arch headers to declare it. Just move the declaration into its own header file and utilize it. Change-Id: I743b4c286956ae047c17fe46241b699feca73628 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13681 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-11arch/{arm64,riscv}: remove jmp_to_elf_entry() declarationAaron Durbin
jmp_to_elf_entry() is not defined anywhere. Remove it. Change-Id: I68f996a735f2ef3dd60cf69f9b72c3f1481cbb55 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11lib/prog_loaders.c: remove arch/stages.h includeAaron Durbin
There's no delcaration used. Remove the include. Change-Id: I6fa7de6362ca0e92f0d5a7d07f3a224b9f77f709 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11arch: remove stage_exit()Aaron Durbin
It's no longer used. Remove it. Change-Id: Id6f4084ab9d671e94f0eee76bf36fad9a174ef14 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-11timestamp: Bump CBMEM timestamp count, make full use of pre-RAM regionsJulius Werner
Since we're reaching the timestamp limit on certain platforms (both for the pre-RAM cache and the final CBMEM region), this patch increases the amount of space for both. In the pre-RAM case, it achieves this by always utilizing the full size of the TIMESTAMP() region allocated in memlayout.ld, rather than arbitrarily limiting it to some constant. BRANCH=None BUG=None TEST=Booted Oak and confirmed that I can once again see all pre-RAM timestamps after picking in the LZ4 patch series. Change-Id: Iabb075a48d8d1e3e1811afeaad5ab47e7846c972 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13651 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLEAndrey Petrov
Early UART driver is for bootblock and romstage. It is supposed to be used when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits in bootblock requiered for serial to be set up. Change-Id: I15520d566f107797e68d618885d4379e73d0fa45 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11soc/apollolake: Add minimal GPIO driverAndrey Petrov
This adds the minimal functionality needed to configure SoC pads. Change-Id: I2e2268eee2b8c822b42a48a95604b0fab86c9833 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-02-11mainboard/intel: Add skeleton for Apollolake RVP board familyAlexandru Gagniuc
RVP1 board comes with DDR3 SODIMMs and discrete VRs. RVP2 board uses LPDDR3 and PMIC. Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11soc/apollolake: Add initial cache-as-ram setup for bootblockAlexandru Gagniuc
This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11cpu/x86/tsc: Compile delay_tsc.c for the bootblock as wellAlexandru Gagniuc
This is needed in a follow-on patch to enable udelay() handling on apollolake, which is a dependency for the console code. Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-11util/marvell: Add Marvell doimage utility and dependency in relevant MakefileRuilin Hao
- Add the doimage sources in util/marvell - Add dependency in root makefile - Add dependency in makefile for armada38x soc BUG=chrome-os-partner:47462 TEST=emerge-cyclone coreboot BRANCH=tot Change-Id: I81b30e0865cbd619a41659c3f2819ad3bafc5f24 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4b2a990150580e0b879a346ed8b71b3765b66bab Original-Change-Id: I7e89b5e96206fde97ce69c296850122fd6c858f9 Original-Signed-off-by: Kefei Yao <kfyao@marvell.com> Original-Reviewed-on: https://chromium-review.googlesource.com/318046 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Kan Yan <kyan@google.com> Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org> Reviewed-on: https://review.coreboot.org/13137 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-11arch/x86: Change how BOOTBLOCK_CUSTOM is selected by defaultAndrey Petrov
Currently x86s select BOOTBLOCK_CUSTOM by default. With this change BOOTBLOCK_CUSTOM is selected only if C bootblock isn't. Change-Id: I218f3b4044175b89697790c82c384b0f85a27ade Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13642 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11arch/x86: Allow bootblock code to use CAR_GLOBAL variablesAndrey Petrov
Since cbmem is not initialized in bootblock, CAR_GLOBAL variables can only be accessed directly similar to verstage. Change-Id: Ifc705016290807c49dc8c49b581864cac2ad3f80 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-11arch/x86: Reserve space for stack in CAR layoutAndrey Petrov
Some platforms may want to use C code in bootblock so they need writable memory and CAR can be used for it. This change reserves memory in CAR that can be used by bootblock and other CAR stages. Change-Id: I8dec768cf8763dbe235f0ba1339079ebc49cbd9a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-02-10cpu/intel/microcode: allow microcode to be loaded in romstageAaron Durbin
The previous usage of the intel microcode support supported using the library under ROMCC and ramstage. Allow for microcode support to be used in normal C-based romstage as well by: 1. Only using walkcbfs when ROMCC is defined. 2. Only using spinlocks if !__PRE_RAM__ The header file now unconditionally exposes the declarations of the supporting functions. Change-Id: I903578bcb4422b4c050903c53b60372b64b79af1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10chromeos/Kconfig: Remove dependency on GBB_HAVE_BMPFVMartin Roth
This symbol is not defined. Change-Id: I2b0a3fca82d85962fc882f237b70702cab0400db Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/13647 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
We want the question for CBFS size to be next to the rom size in the mainboard directory, but that doesn't seem to work for how people want to set the defaults. Instead of having the list of exceptions to the size, just set the defaults at the end of kconfig. - Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into the chipset Kconfigs (gm45, nehalem, sandybridge, x4x) - Override the default for HAVE_INTEL_FIRMWARE on skylake. - Move the HAVE_INTEL_FIRMWARE default setting into the firmware Kconfig file - Move the location of the default CBFS_SIZE=ROM_SIZE to the end of the top level kconfig file, while leaving the question where it is. Test=rebuild Kconfig files before and after the change, verify that they are how they were intended to be. Note: the Skylake boards actually changed value, because they were picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the 0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after the HAVE_INTEL_FIRMWARE default. Affected boards were: Google chell, glados, & lars and Intel kunimitsu. Change-Id: I2963a7a7eab037955558d401f5573533674a664f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10intel/fsp1_0: Allow the MRC cache to live in a FMAP regionBen Gardner
The new option CONFIG_MRC_CACHE_FMAP will cause fastboot_cache.c to look in the FMAP for a region named "RW_MRC_CACHE" and prevents adding a CBFS file named "mrc.cache". Tested on a fsp_baytail-based board. Change-Id: I248f469c7e3447ac4ec7be32229fbb5584cfd2ed Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/13632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10google/veyron_speedy: remove extraneous filePatrick Georgi
veyron_speedy was deduplicated as sub-board into google/veyron, so the addition of chromeos.fmd (identical btw) wasn't useful. Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10google/chromeos: backup -> back upPatrick Georgi
See discussion on https://review.coreboot.org/13600 and https://review.coreboot.org/13601 Change-Id: Ia8274b0b296d6b398f75c0d91a6fded4c5f57e10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13643 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-10arch/arm64: Use correct SPSR.DAIF mask for BL31 and payloadJulius Werner
The PSTATE mask bits for Debug exceptions, external Aborts, Interrupts and Fast interrupts are usually best left unset: under normal circumstances none of those exceptions should occur in firmware, and if they do it's better to get a crash close to the code that caused it (rather than much later when the kernel first unmasks them). For this reason arm64_cpu_init unmasks them right after boot. However, the EL2 payload was still running with all mask bits set, which this patch fixes. BL31, on the other hand, explicitly wants to be entered with all masks set (see calling convention in docs/firmware-design.md), which we had previously not been doing. It doesn't seem to make a difference at the moment, but since it's explicitly specified we should probably comply. BRANCH=None BUG=None TEST=Booted Oak, confirmed with raw_read_daif() in payload that mask bits are now cleared. Change-Id: I04406da4c435ae7d44e2592c41f9807934bbc802 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ba55bc23fbde962d91c87dc0f982437572a69a8 Original-Change-Id: Ic5fbdd4e1cd7933c8b0c7c5fe72eac2022c9553c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/325056 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10arch/arm64: mmu: Spot check TTB memory attributesJulius Werner
On ARM64, the memory type for accessing page table descriptors during address translation is governed by the Translation Control Register (TCR). When the MMU code accesses the same descriptors to change page mappings, it uses the standard memory type rules (defined by the page table descriptor for the page that contains that table, or 'device' if the MMU is off). Accessing the same memory with different memory types can lead to all kinds of fun and hard to debug effects. In particular, if the TCR says "cacheable" and the page tables say "uncacheable", page table walks will pull stale entries into the cache and later mmu_config_range() calls will write directly to memory, bypassing those cache lines. This means the translations will not get updated even after a TLB flush, and later cache flushes/evictions may write the stale entries back to memory. Since page table configuration is currently always done from SoC code, we can't generally ensure that the TTB is always mapped as cacheable. We can however save developers of future SoCs a lot of headaches and time by spot checking the attributes when the MMU gets enabled, as this patch does. BRANCH=None BUG=None TEST=Booted Oak. Manually tested get_pte() with a few addresses. Change-Id: I3afd29dece848c4b5f759ce2f00ca2b7433374da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f3947f4bb0abf4466006d5e3a962bbcb8919b12d Original-Change-Id: I1008883e5ed4cc37d30cae5777a60287d3d01af0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323862 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13595 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-10soc/intel/quark: Report CPU infoLee Leahy
Decode the CPU variants and display the CPU info. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Successful if Quark X1000 is displayed Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13605 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/intel/quark: Call FSP SiliconInitLee Leahy
Optionally relocate FSP into DRAM and then call FSP SiliconInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_FSP_ENTRY_POINTS" * Add "select DISPLAY_HOBS" * Optionally add "select RELOCATE_FSP_INTO_DRAM" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * FSP entry points are displayed and * The message "FspSiliconInit returned 0x00000000" is displayed and * The HOBs are displayed correctly and * The message "ERROR - Missing one or more required FSP HOBs!" is not displayed Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13631 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10soc/intel/quark: MTRR supportLee Leahy
Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2016-02-10soc/fsp_baytrail: Add support for FSP MR 005Ben Gardner
Baytrail FSP MR 005 adds two new fields: AutoSelfRefreshEnable APTaskTimeoutCnt Add the device tree definitions. Change-Id: I12e2a8b0b5cbeb6b7289cf91f65b25e73007a8de Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12973 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
2016-02-10soc/intel/quark: FSP MemoryInit SupportLee Leahy
Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_HOBS" * Add "select DISPLAY_UPD_DATA" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13447 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09ASL: Remove unused modulo recipient.Vladimir Serbinenko
Change-Id: I4b0a3073815ec8d98c2d23cd745f027517b6fa42 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13619 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09stout: Add native gfx initVladimir Serbinenko
Tested during FOSDEM. Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13532 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
In the same time remove few native gfx options which were improperly set and only added dead code to the binary. Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13649 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-09rockchip/rk3288: UART uses 32bit wide registersPatrick Georgi
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13635 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09vboot2: Store depthcharge graphic assets only in ROPatrick Georgi
These files aren't updated (or updatable), and as such don't need to be copied to the RW sections. Change-Id: Ie78936792ad651fbf8500fc7e34f0899e33a904c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09ivy: Add a possiblity for mainboard early init.Vladimir Serbinenko
This is needed for stout EC init. Change-Id: I5c73499c17763229840152a473a2d820802ee2f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13535 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09superio/nuvoton/nct5572d: Add PS/2 presence detectPaul Menzel
On certain Super I/O devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. This is added in commit 448e3863 (drivers/pc80: Add PS/2 mouse presence detect). Update the Nuvoton NCT5572D driver to flag the auxiliary channel as disabled if no device was detected. The code is copied from the Winbond W83667HG-A driver. Note, the ACPI changes are not part of this commit. TEST=Currently, on the ASRock E350M1, PS/2 does not work. With this change, a PS/2 keyboard works fine in SeaBIOS, GRUB in MBR, and Debian GNU/Linux Sid/unstable with Linux 3.19. ``` [ 1.185195] i8042: PNP: No PS/2 controller found. Probing ports directly. [ 1.189110] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.189133] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.189970] mousedev: PS/2 mouse device common for all mice ``` Change-Id: I7f9be348d295e70437bef089d4c2173169f38459 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/13618 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09Kconfig: Move payloads section to payloads/KconfigMartin Roth
Move the payloads section of the kconfig tree out of the top level kconfig file and into a separate Kconfig just for payloads before it starts to get added to. Change-Id: I4f52818f862bf1aeba538c1c6ed93211a78b9853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13608 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-09Revert "northbridge/intel/peg: Disable unused ports"Nico Huber
This reverts commit 0e06f5bd70b45fd330d8dfb1dc77cce043caf841. It breaks gm45 and also does some magic without being asked too. It disables bridge devices permanently if no device was found on the se- condary bus. In a simple notebook world this might be ok, but it breaks hot-plugging and late detection (if a secondary bus device comes up too slow for the firmware to detect and the OS has to enumerate it). Change-Id: Ia2010640d7c55b0bdd44164b81c75dd4be50410b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/13609 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-09Workaround for unused variable warning.Vladimir Serbinenko
Change-Id: I0a0c925509027f98f724d0a4347146f21ac06c02 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13624 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09ASL: Use temporary variable when storing register into itself.Vladimir Serbinenko
Otherwise it triggers a IASL warning with new IASL. Change-Id: I090ee18df78ea779137ee6797c55b96ea27e6d27 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13623 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09ASL: Fix HPBA shadowing.Vladimir Serbinenko
Store (HPBA, HPBA) had no effect. Rename one of HPBA to avoid shadowing. Change-Id: I54bfa7bcb3e05c28fe8a257825af56527dbf663e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13622 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09rx886ex: Fix PBIF reference.Vladimir Serbinenko
PBIF is package and so a scalar can't be stored instead of it. What was meant is probably Index(PBIF, 0) Change-Id: Iddd18e1f165e0f48fd91124200aba5c6b4a5b4bd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09ASL: Remove unused local variables.Vladimir Serbinenko
Change-Id: Ifcbb6916b718d41fb9cda537ffdc3e652e13cbbf Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13620 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09stout: Fix ASL warningsVladimir Serbinenko
Change-Id: I1ddf37aa61fe95ad632c35d8041aed02fb1e8c01 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13533 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09mainboard/lenovo: Add support for the Lenovo ThinkPad X220iChristopher Spinrath
The ThinkPad X220i is essentially identical to the ThinkPad X220 but it has a Sandybridge i3 (instead of a Sandybridge i5/i7) CPU and the VGA_BIOS_ID differs. Thus, support is added by using the X220 mainboard directory and setting the VGA_BIOS_ID in Kconfig. Change-Id: I33345a099c617e8c87a1de64b7254b7e7716ca90 Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-on: https://review.coreboot.org/13594 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-02-09intel/kunimitsu: Clean up GPIOs.Pratik Prajapati
Some of the pins are not connected/used on kunimitsu board, this patch will make them "Not connected". Un-used PINS will controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BRANCH=none BUG=none TEST=Build and booted in kunimitsu. Change-Id: Iaf0d4806836648808fb91cfc7807c4c1595a5167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7c25ad8ee0d189178124cff20569152b1053488 Original-Change-Id: I3add625b2bf01223cd389c6a5585827ac62dd0c0 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316700 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/13629 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09intel/skylake: Add gpio macro for unused GPIO pinsdavid
Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. BUG=none BRANCH=none TEST=Build and boot lars Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9 Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319964 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/13628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09build system: Build Chrome EC firmware on requestPatrick Georgi
With the Chrome EC's "board" name set in Kconfig, the build system will build and add the EC firmware, too. Available for the EC and the USB PD controller. Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13547 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09mb/intel/d510mo: Explicitly select NIC on PCI in devicetreeDamien Zammit
While the board configuration still works without this, It's nicer to have the device statically defined since the NIC is hardwired to the board. Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13455 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09console: Disable SQUELCH_EARLY_SMP if SMP is not selectedLee Leahy
Add a "depends on SMP" to the value SQUELCH_EARLY_SMP Kconfig value to disable its selection when SMP is not enabled. TEST=Build for Galileo Change-Id: Ia3aa1d2169ed793e1bb26538b74b12347453d5af Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13639 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09soc/intel/quark: Enable Serial PortLee Leahy
Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13445 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 12:23:01 +0000