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2017-03-22soc/intel/skylake: Add configs for enabling DCI and TraceHubAamir Bohra
Add configs for enabling Intel TraceHub and DCI for aid in debugging. Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22soc/intel/apollolake: Add CQOS config for CAR common codeSubrata Banik
Change-Id: I5947170a96e888cea2f3faac92355e72b63c1fef Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22mainboard/google/reef: add nasher variantYH Lin
Create the initial Nasher variant which refers to the Reef. Nasher is APL board that derives from reference board Reef. BRANCH=master BUG=b:36389286 TEST=Build (as initial setup) Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: I7962aa8246890149988c7f02dcd90d820df7b901 Reviewed-on: https://review.coreboot.org/18928 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21google/pyro: Update DPTF settingsKevin Chiu
1. correct DPTF TCHG target device to TSR2 2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18920 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21mainboard/google/poppy: Use sideband IRQ for SD Card DetectFurquan Shaikh
Since SD card controller is expected to enter D3hot by runtime power management if there is no card inserted, we need to use a sideband IRQ pin which is not under the control of the controller. Thus, configure GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect pin. BUG=b:35586693 BRANCH=None TEST=Verified on a reworked poppy board that card detect works fine. Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18926 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-21nb/x4x: Move checkreset before SPD readingArthur Heymans
It makes no sense to read SPDs if the system will reset anyway. Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17661 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-21nb/intel/x4x: Fix issues found by checkpatch.plArthur Heymans
Change-Id: Ie22b8bd5420f8c33df1866410af42ef41ad38362 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18694 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-21mainboards: Don’t select `CONSOLE_POST`Paul Menzel
Currently, it’s impossible for the user to select `NO_POST`, for boards selecting `CONSOLE_POST` in their config. ``` warning: (BOARD_SPECIFIC_OPTIONS) selects CONSOLE_POST which has unmet direct dependencies (VENDOR_SIEMENS && BOARD_SIEMENS_MC_BDX1 || !NO_POST) ``` This is currently done for Intel Camelback Mountain and Siemens MC-BDX1. Selecting the option `CONSOLE_POST` in board specific configuration is not a good idea, as this should be user configurable over Kconfig, and also the tree-wide defaults should be the same for these options. Kconfig is different, as commit 97535558f1 (mainboard/{google,intel}: Change config option selection) only touch the Intel board. Change-Id: I91c1e0cb92ed218b6bbc7c33759b91f748cf6f51 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18878 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-03-21mainboards: Don’t select `POST_IO`Paul Menzel
Currently, it’s impossible for the user to select `NO_POST`, for boards selecting it in their config. ``` warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS) selects POST_IO which has unmet direct dependencies (VENDOR_ASUS && (BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE) && (BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO) || VENDOR_MSI && BOARD_MSI_MS7721 || PC80_SYSTEM && !NO_POST) ``` This is currently done for Intel Mohon Peak, and its descendants. Selecting the option `POST_IO` in board specific configuration is not a good idea, as this should be user configurable over Kconfig, and also the tree-wide defaults should be the same for these options. Change-Id: Ia4ab0d942b7d66f18466a770ef739109ab0db629 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18877 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-21southbridge/nvidia/mcp55: Get rid of #include early_smbus.cArthur Heymans
Using linker instead of '#include *.c'. Change-Id: I74dfa99c8bb3f4ca7ef3d774be2197897022f52c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18484 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-21soc/intel/apollolake: Use common function to fill DIMM informationBarnali Sarkar
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and use common function dimm_info_fill() to save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot Reef to verify the type 17 DIMM info coming in SMBIOS table from Kernel command "dmidecode". Change-Id: I33c3a0bebf33c53beadd745bc3d991e1e51050b7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18451 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-03-21ec/lenovo/h8: Support an optional battery page flip delayTobias Diedrich
The Lenovo H8 battery interface uses a paged EC memory area. Some Thinkpads (in particular the S230U) use a different EC controller (ENE KB9012) with mostly compatible firmware, which requires an explicit delay between writing the page register and reading the page data. Change-Id: Iaeb8c4829efa29139396b519de803f10dd93f03f Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18348 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-21emulation/qemu-i440fx: Use SMBIOS macrosPaul Menzel
Change-Id: Idda4d74f9b934ccefe6ea5b553bde587059cde64 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18790 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-21google/sand: Add Raydium touchscreen deviceKatherine Hsieh
We just support Raydium touchscreen instead of Elan. Thus we have to remove Elan touchscreen device and add Raydium touchsrcreen device. BUG=b:35775065 BRANCH=reef TEST=emerge-sand coreboot Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-20mb/apple/macbook11,macbook21,imac52: Remove per board directoriesArthur Heymans
This is achieved by setting up Kconfig and Kconfig.name very similar to how variants are used. Change-Id: I22089ff29e3879d7956527a092a0ac6425b05cb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17894 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-20arch/x86: Fix most of remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: do not use assignment in if condition ERROR: trailing statements should be on next line ERROR: Macros with complex values should be enclosed in parentheses ERROR: switch and case should be at the same indent WARNING: char * array declaration might be better as static const WARNING: else is not generally useful after a break or return WARNING: storage class should be at the beginning of the declaration WARNING: void function return statements are not generally useful WARNING: break is not useful after a goto or return WARNING: Single statement macros should not use a do {} while (0) loop WARNING: sizeof *t should be sizeof(*t) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I39d49790c5eaeedec5051e1fab0b1279275f6e7f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-20mainboard/google/snappy: Update _hid name for weida touchscreenWisley Chen
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by standard hid i2c Linux driver. BUG=b:35586513 BRANCH=reef TEST=build, boot on snappy, and verified acpi node "WDHT0002" created. Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18874 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-19mb/google/reef: Remove CPU throttling effect of the charger sensorSumeet Pawnikar
It's not relevant to throttle CPU based on the charger sensor. So, remove this CPU throttling effect. BUG=b:35908799 BRANCH=master TEST=Built and booted on Electro DUT Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/18852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-03-19cpu/x86: add a barrier with timeoutBora Guvendik
In case something goes wrong on one of the cpus, add the ability to use a barrier with timeout so that other cpus don't wait forever. Remove static from barrier wait and release. BUG=chrome-os-partner:59875 BRANCH=reef TEST=None Change-Id: Iab6bd30ddf7632c7a5785b338798960c26016b24 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/18107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-19ramstage: Align stack to 16 bytesKyösti Mälkki
Some SSE instructions could take 128bit memory operands from stack. AGESA vendorcode was always built with SSE enabled, but until now stack alignment was not known to cause major issues. Seems like GCC-6.3 more likely emits instructions that depend on the 16 byte alignment of stack. Change-Id: Iea3de54f20ff242105bce5a5edbbd76b04c0116c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18823 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-19sb/intel/common/firmware: Add Intel ME/TXE firmware checkNicola Corna
Ensure that the provided ME/TXE firmware is valid, using the check capabilities of me_cleaner. me_cleaner checks that the fundamental partition is available and it has a correct signature. The checks performed by me_cleaner aren't exhaustive, but they should find at least whether the user has provided an empty or corrupted firmware. me_cleaner has been tested on all the ME (6-11.6) and TXE (1-3) firmwares available here [1], and it hasn't reported any false positive. [1] http://www.win-raid.com/t832f39-Intel-Engine-Firmware-Repositories.html Change-Id: Ie6ea3b4e637dca4097b9377bd0507e84c4e8f687 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18768 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-18nb/i945/gma.c: Refactor panel setupArthur Heymans
This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-17drivers/intel/fsp1_1: Fix issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" WARNING: line over 80 characters WARNING: else is not generally useful after a break or return WARNING: braces {} are not necessary for single statement blocks WARNING: suspect code indent for conditional statements (16, 32) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18886 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-17soc/intel/broadwell: Fix other issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent WARNING: line over 80 characters WARNING: storage class should be at the beginning of the declaration WARNING: adding a line without newline at end of file WARNING: __func__ should be used instead of gcc specific __FUNCTION__ WARNING: Comparisons should place the constant on the right side of the test TEST=None Change-Id: I85c400e4a087996fc81ab8b0e5422ba31df3c982 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18885 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/broadwell: Fix {}, () and conditional issuesLee Leahy
Fix the following errors and warnings detected by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: return is not a function, parentheses are not required ERROR: do not use assignment in if condition ERROR: trailing statements should be on next line WARNING: else is not generally useful after a break or return WARNING: braces {} are not necessary for single statement blocks WARNING: braces {} are not necessary for any arm of this statement TEST=None Change-Id: I9414341b0c778c252db33f0ef4847b9530681d96 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18884 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/broadwell: Add int to unsignedLee Leahy
Fix the following issue detected by checkpatch: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=None Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18873 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-17soc/intel/broadwell: Fix spacing issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '<=' (ctx:VxV) ERROR: spaces required around that '>' (ctx:VxV) ERROR: spaces required around that '>=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" ERROR: space required before the open parenthesis '(' WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no space before tabs WARNING: please, no spaces at the start of a line False positives are generated for the following test: WARNING: space prohibited between function name and open parenthesis '(' in both pei_data.h and pei_wrapper.h TEST=None Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18872 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17google/veyron: Clean out unused board variantsJulius Werner
We have code for certain Veyron variant names that were either never made into an actual board (Gus, Nicky, Thea) or used for Google-internal test boards that no longer exist (Pinky, Shark). Let's clean them out to avoid confusing people. Change-Id: Icdce5f0f3613e089d0994318b02dba54170f0c42 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-17google/veyron: Work around RAM code strapping errorJulius Werner
With a recent patch (google/veyron_*: Add new Micron and Hynix modules) we switched RAM codes for Veyron boards to tri-state since we were running out of binary numbers. Unfortunately we only tested that change on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and Mighty. The "high" RAM code pins on those boards were incorrectly strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and Speedy), which is too high to overpower the SoC-internal pull-down we use to differentiate "high" from "tri-state". Since we already used tri-state codes on some Minnie and Speedy SKUs we have to hack up the code to work differently on these two groups of boards to keep everything working. BRANCH=veyron BUG=b:36279493 TEST=Compiled, confirmed ram_code called the right function depending on board. Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18859 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-17mainboard/google/poppy: Enable EC SW syncFurquan Shaikh
Now that EC on poppy is stable, it is time to switch on EC SW sync. BUG=b:36178824 BRANCH=None TEST=Verified that EC SW sync is done properly and device boots to OS. Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18838 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/apollolake: Reduce D3 cold delay for eMMC controllerZhuo-hao Lee
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Apollo Lake system such as Snappy. The cause is the Linux Kernel setting the firmware reset time to 100 ms by default. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update snappy coreboot and test i/o latency is under 100ms Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a Reviewed-on: https://review.coreboot.org/18806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-17arch/x86: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18864 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix prefer errors detected by checkpatchLee Leahy
Fix the following warnings detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: plain inline is preferred over __inline__ TEST=Build and run on Galileo Gen2 Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18863 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix space issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited after that open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: space prohibited after that open square bracket '[' ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ';' (ctx:VxV) ERROR: spaces required around that ':' (ctx:ExV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: spaces required around that ':' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that '+=' (ctx:VxV) ERROR: spaces required around that '<=' (ctx:WxV) ERROR: spaces required around that '||' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxO) ERROR: need consistent spacing around '+' (ctx:WxV) ERROR: spaces required around that '<' (ctx:WxV) ERROR: spaces required around that '<' (ctx:VxV) ERROR: need consistent spacing around '>>' (ctx:WxV) ERROR: "(foo*)" should be "(foo *)" ERROR: "foo* bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: unnecessary whitespace before a quoted newline WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs WARNING: Unnecessary space before function pointer arguments TEST=Build and run on Galileo Gen2 Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17arch/x86: Fix issues with braces detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line ERROR: that open brace { should be on the previous line ERROR: else should follow close brace '}' WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build and run on Galileo Gen2 Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18861 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17soc/intel/braswell: Fix most of the issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: that open brace { should be on the previous line ERROR: return is not a function, parentheses are not required WARNING: braces {} are not necessary for any arm of this statement WARNING: line over 80 characters WARNING: braces {} are not necessary for single statement blocks WARNING: Avoid unnecessary line continuations WARNING: break is not useful after a goto or return WARNING: else is not generally useful after a break or return False positives are generated by checkpatch for the following test: ERROR: Macros with complex values should be enclosed in parentheses TEST=Build for cyan Change-Id: I19048895145b138a63100b29f829ff446ff71b58 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18871 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/braswell: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for cyan Change-Id: Ib5c6a1bf5308a8add42d7371854b80ea53d7ae84 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18870 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/braswell: Fix spacing issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: space required after that ',' (ctx:VxV) ERROR: space prohibited before that ',' (ctx:WxE) ERROR: spaces required around that '=' (ctx:WxV) ERROR: code indent should use tabs where possible WARNING: space prohibited between function name and open parenthesis '(' WARNING: please, no spaces at the start of a line TEST=Build for cyan Change-Id: I84d4204585b498b695608c5008fdfb7961e2416f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18869 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-03-17soc/intel/skylake: Fix remaining issues detected by checkpatchLee Leahy
Fix the following errors and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible ERROR: Macros with complex values should be enclosed in parentheses ERROR: "foo * bar" should be "foo *bar" ERROR: space required before the open parenthesis '(' ERROR: spaces required around that '=' (ctx:VxW) WARNING: space prohibited between function name and open parenthesis '(' WARNING: storage class should be at the beginning of the declaration WARNING: char * array declaration might be better as static const WARNING: please, no space before tabs WARNING: braces {} are not necessary for single statement blocks WARNING: else is not generally useful after a break or return WARNING: static const char * array should probably be static const char * const TEST=Build for glados Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18868 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-17soc/intel/skylake: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2017-03-17soc/intel/skylake: Add int to unsignedLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for glados Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-16google/poppy: Use rt5663 interrupt as GpioInt instead of PIRQRizwan Qureshi
The kernel driver for rt5663 expects to get an interrupt on both a rising and falling edge, and using a legacy interrupt doesn't provide that flexibility. Instead configure this pin as a GPIO and use the interrupt through the GPIO controller. This allows using GpioInt() with ActiveBoth setting and results in correct operation of the headset jack. This is a clone of Duncan's patch for eve at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529 BUG=none BRANCH=none TEST=test on poppy that headset jack detect is read properly at boot, and that plugging in and removing both generate a single interrupt event in the driver. Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16google/eve: Use rt5663 interrupt as GpioInt instead of PIRQDuncan Laurie
The kernel driver for rt5663 expects to get an interrupt on both a rising and falling edge, and using a legacy interrupt doesn't provide that flexibility. Instead configure this pin as a GPIO and use the interrupt through the GPIO controller. This allows using GpioInt() with ActiveBoth setting and results in correct operation of the headset jack. BUG=b:35585307 BRANCH=none TEST=test on Eve that headset jack detect is read properly at boot, and that plugging in and removing both generate a single interrupt event in the driver. Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18836 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16i2c/generic: Add support for GPIO IRQDuncan Laurie
Add support for using GPIO IRQ instead of PIRQ with an I2C device. This allows a device to use an edge triggered interrupt that will trigger on both high and low transitions. The _DSD method for describing these GPIOs has a field for 'active low' which is supposed to be 1 if the pin is active low, otherwise is zero. The value in here doesn't mean too much for GpioInt() as those will end up using the value from GpioInt() when it actually requests the interrupt. BUG=b:35581264 BRANCH=none TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18835 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16acpi_device: Add macro for GpioInt that uses both polarityDuncan Laurie
GPIO edge interrupts can report that they are ActiveBoth and will generate an interrupt event on both rising and falling edges. Add a macro so this type of GPIO interrupt can be used. BUG=b:35581264 BRANCH=none TEST=successfully use this interrupt type on Eve Change-Id: I91408386538e442bddcacc9840e0aa14370a446c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-16acpi_device: Prefix IRQ macros with ACPIDuncan Laurie
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not fail at compile time if they are used. BUG=b:35581264 BRANCH=none TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18833 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-16binaryPI: Fix SSE regression and align stack earlyKyösti Mälkki
When allowing use of SSE instructions, stack must be aligned to 16 bytes. Adjust x86 entry to C accordingly, by pushing values to maintain the alignment. For some builds, new toolchain and GCC-6.3 could emit SSE instruction 'andps (%esp),%xmm0' with incorrectly aligned esp, raising exception and thus preventing boot. Change-Id: I452d40eadac2b743d0d8431809c9a81bf28c330a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-03-16asrock/e350m1: Include ASL for PS/2 controllerPaul Menzel
On the ASRock E350M1, with Linux 4.10 after resuming from S3, the PS/2 keyboard does not work. Adding the ASL code, fixes this. The Linux messages change like below. Before (equivalent to `i8042.nopnp`): ``` kernel: i8042: PNP: No PS/2 controller found. kernel: i8042: Probing ports directly. kernel: serio: i8042 KBD port at 0x60,0x64 irq 1 kernel: serio: i8042 AUX port at 0x60,0x64 irq 12 kernel: mousedev: PS/2 mouse device common for all mice ``` After: ``` kernel: i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1 kernel: i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp kernel: serio: i8042 KBD port at 0x60,0x64 irq 1 kernel: mousedev: PS/2 mouse device common for all mice ``` Change-Id: I0a06311860398cac9cf1a077e3aba75da779f45d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/18574 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-03-16cpu/intel: Fix the remaining issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent WARNING: Consecutive strings are generally better as a single string WARNING: static const char * array should probably be static const char * const TEST=Build and run on Galileo Gen2 Change-Id: I03d5d0d2db0d5e9b33c8ec807b236fe229bcc8f3 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-16cpu/intel: Wrap lines at 80 columnsLee Leahy
Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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