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2021-04-14mb/google/volteer: Add GPIO to collis supportFrankChu
Add support for gpio driver for collis BUG=b:182227204 TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ief225093bf93137384b64327a1c66576c9a5193a Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-14mb/system76/whl-u: Add System76 Galago Pro 3 Rev CTim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - NVMe port - SATA port - SD card slot - Left USB 3 Type-A port - Right USB 3 Type-A port - Right USB 3 Type-C port - Webcam - Ethernet - Integrated graphics using Intel GOP driver - mDP output - HDMI output - Internal microphone - Internal speakers - 3.5mm audio input - 3.5mm audio output - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux 20.10 and Windows 10 Not tested: - Thunderbolt functionality Change-Id: I5c992e603dbd57ae1b4ddc3a0f9bfc92d6acc813 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/amd/stoneyridge: use common pm_set_power_failure_state functionalityFelix Held
The functionality to restore the previous power state after power was lost that could previously be enabled by selecting MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's Kconfig instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49c4a44ca2c4fa937a823c4eddf1618739c15114 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/piasso/fch: use common pm_set_power_failure_state functionalityFelix Held
The functionality to restore the previous power state after power was lost that could previously be enabled by selecting MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's Kconfig instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: rework pm_set_power_failure_stateFelix Held
Picasso and Stoneyridge didn't do a read-modify-write operation on the lower nibble of PM_RTC_SHADOW_REG, but just wrote the upper nibble as all zeros. Since the upper nibble might be uninitialized before the lower nibble gets written, do what Picasso and Stoneyridge did here instead of what the reference code does. Also add a comment why and how this register behaves a bit weird. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bda2349e3ae84cba50b187cc773fd8a5b17f4e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: remove POWER_STATE_DEFAULT_ON_AFTER_FAILUREFelix Held
Not selecting POWER_STATE_DEFAULT_ON_AFTER_FAILURE brings Cezanne that is currently the only SoC using this functionality in line with Picasso where the default is that the board remains in power off mode after power was lost and later restored. Boards can change this behavior by selecting POWER_STATE_OFF_AFTER_FAILURE, POWER_STATE_ON_AFTER_FAILURE or POWER_STATE_PREVIOUS_AFTER_FAILURE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic96f40e3c9867cd821e58d752f58b763930f6d0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/common/block/pm: select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILUREFelix Held
Without this being selected, mainboards can't select MAINBOARD_POWER_STATE_PREVIOUS to use the power state restoration code path in pmlib.c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I753659fa753e03a66b6c6b2eb97e7ef20c71ca57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14mb/google/brya: Enable CSE Lite SKUTim Wawrzynczak
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:183826781 TEST=50 cold reboot cycles Cq-Depend: chrome-internal:3758108 Change-Id: Ib3a1a9f8ac51bdab8858b2764d5bc0f6f07987cc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-14mb/portwell/m107/Kconfig: Remove CACHE_MRC_SETTINGSFrans Hendriks
The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig. BUG = N/A TEST = Build and boot Portwell M107 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I528c582419fb2044f5edfd7a070785489efdf7a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52154 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14lillipup: provide additional VBT for lillipup OLED skuKevin Chang
Lillipup add two sku for OLED panel. Additional VBT is necessary to modify PWM source from VESA eDP AUX interface BUG=b:183630802 TEST=emerge-volteer coreboot-private-files-baseboard-volteer check vbt_oled.bin is under build folder and check in CPU log. Cq-Depend: chrome-internal:3744227 Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I576297b8296def3c37a01ae0223fa332aa9f02b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52150 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14Rename do_printk() to printk()Nico Huber
The indirection seems unnecessary. The macros throw features like `-Wmisleading-indentation` off, though. Default build for QEMU/Q35 is unchanged. Change-Id: Ie4eab935a367b5ad6b38225c4973d41d9f70ef10 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-14console: Always add printf-format attribute to printk()Nico Huber
The attribute was missing in case the console is disabled. Change-Id: Iee23f6f4da61cd3637441705a8d3bbd2da7a33ca Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52231 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14intel: mma: Use new CBFS APIJulius Werner
This patch changes the Intel MMA driver to use the new CBFS API. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-14intel: fsp2_0: Move last pieces to new CBFS APIJulius Werner
This patch ports the last remaining use of cbfs_boot_locate() in the Intel FSP drivers to the new CBFS API. As a consequence, there is no longer a reason for fsp_validate_component() to operate on rdevs, and the function is simplified to take a direct void pointer and size to a memory-mapping of the FSP blob instead. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If1f0239eefa4542e4d23f6e2e3ff19106f2e3c0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52281 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14vboot: ec_sync: Switch to new CBFS APIJulius Werner
This patch changes the vboot EC sync code to use the new CBFS API. As a consequence, we have to map the whole EC image file at once (because the new API doesn't support partial mapping). This should be fine on the only platform that uses this code (Google_Volteer/_Dedede family) because they are x86 devices that support direct mapping from flash, but the code was originally written to more carefully map the file in smaller steps to be theoretically able to support Arm devices. EC sync in romstage for devices without memory-mapped flash would be hard to combine with CBFS verification because there's not enough SRAM to ever hold the whole file in memory at once, but we can't validate the file hash until we have loaded the whole file and for performance (or TOCTOU-safety, if applicable) reasons we wouldn't want to load anything more than once. The "good" solution for this would be to introduce a CBFS streaming API can slowly feed chunks of the file into a callback but in the end still return a "hash valid/invalid" result to the caller. If use cases like this become pressing in the future, we may have to implement such an API. However, for now this code is the only part of coreboot with constraints like that, it was only ever used on platforms that do support memory-mapped flash, and due to the new EC-EFS2 model used on more recent Chrome OS devices we don't currently anticipate this to ever be needed again. Therefore this patch goes the easier way of just papering over the problem and punting the work of implementing a more generic solution until we actually have a real need for it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7e263272aef3463f3b2924887d96de9b2607f5e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52280 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/mediatek: Include sdram_info in ddr_base_infoYu-Ping Wu
Sync dramc_param.h with private repo mtk-dramk (CL:*3751861). BUG=none TEST=emerge-asurada coreboot TEST=Hayato boots with fast calibration BRANCH=asurada Change-Id: I79541f66ce68a75147c22b83a456e6268ca1485e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-04-14mb/google/cherry: Add MediaTek MT8195 reference boardYidi Lin
TEST=boot from SPI-NOR and UART works fine. Change-Id: I279b3d2da8a30b38686005212f6c019a9a646874 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-14soc/amd/picasso/fch: add missing amdblocks/gpio_banks.h headerFelix Held
The prototype of gpio_add_events() is provided by that header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia384c9297ac1e24bf0b1bcce048012a247406f39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO eventsFelix Held
BUG=b:184549804 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ebbe9667d18a96b1a363d0353c612e214699d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52273 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-14soc/amd/cezanne: save chipset state to CBMEMMartin Roth
Guybrush complains that this is missing during the boot, so add it to cezanne. I verified that the registers in gpio.c are correct. BUG=b:184549804 TEST=Build and boot Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-14soc/amd/picasso/romstage: factor out chipset state saving functionalityFelix Held
Since Cezanne needs the exact same code, move it to the common directory and add a Kconfig option to add this functionality to the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-13mb/clevo/cml-u: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entry from clevo/cml-u, which has been forgotten in commit c5f1dc9. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I05844db4cfe96e6075bd6526ffc242973a2082c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-13mb/hp/280_g2/romstage.c: Correct CaVrefConfig settingAngel Pons
With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1. Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-13dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak
DPTF HIDs are different per-platform going forward, so refactor these into SoC-specific structures which the DPTF driver can query at runtime for platform-specific information. Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoCYidi Lin
TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-12nb/intel/x4x: Refactor sync DLL programming (part 2)Nico Huber
Instead of counting consecutive matches (in `j`), check for a second match directly in the control flow. Also, add some dedicated variables: * `tap`: Keeps track of the tap value that resulted in a match and is eventually programmed into the hardware. * `tap2`: Is just temporarily used to search for another edge. Keeping `tap` sync'ed with the hardware has the benefit that we don't need to read the programmed value back for later fixups. Change-Id: I3ae541c39efdc695f5ca74bc757b2f009239ec93 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12nb/intel/x4x: Refactor sync DLL programming (part 1)Nico Huber
Extract some common code patterns into functions. Change-Id: I5f8d40bb55d4b4f0639e0287881ae0ecde298590 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-12nb/intel/x4x: Sort code in program_dll()Nico Huber
Move the last block of the sync DLL programming up. It's independent of the switch/case statement that it's moved around. Change-Id: I71bc1ca1c629e4f2f4a13474c7e2c22d1a3b65d9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-12mb/google/mancomb: Temporary fix to set eSPI muxEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-12chromeec: make ssfc optional in fw_configKangheui Won
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, all fw_config is invalidated. But for some platform this may not be necessary, we can treat missing SSFC as zero and use other 32 bits of firmware config. BUG=b:184809649 TEST=boot and check fw_config is not -1 even if ssfc is not set BRANCH=zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-12mb/*: drop LPC generic range for port 80Michael Niewöhner
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12mb/amd/majolica/port_descriptor: use GPIO number defineFelix Held
TEST=Timeless build results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie39dc99bef4eb3776388d7406239bac6031bfaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/52193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-12mb/google/mancomb: add DXIO and DDI descriptorsEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-12mb/amd/bilby: Use Picasso VBIOS as defaultRitul Guru
use PicassoGenericVbios.bin as default instead of raven VBIOS for Bilby. Change-Id: I99621173a33a1154f8bb4929d199288265bbe04d Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52209 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11mb/google/dedede: Enable HECIAseda Aboagye
This commit enables HECI such that interface can be used from userspace on the dedede mainboards. BUG=b:184219504 TEST=Build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I5b28c471d6554a5e14538073d48ef47da05936fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-11soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_stateFelix Held
Verified that all accessed registers exist in all SoCs that use this code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment) and that the bit definitions match as well. Also at the time of writing this patch only Picasso calls gpio_fill_wake_state, so dropping the check won't change behavior. This also avoids having SoC specific code that doesn't get selected by Kconfig options in the common AMD SoC directory and also avoids having to add a check for SOC_AMD_CEZANNE to support this functionality on Cezanne in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If770780a67776daf81744db1b635ffd402653a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11sb/amd/pi/hudson: remove unused Bolton PI FCH codeFelix Held
There is no nb/amd/pi northbridge left in coreboot that could be paired with the Bolton FCH, since the remaining nb/amd/pi northbridges all use an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton is a discrete FCH. I ran into this when verifying if the common soc/amd GPIO functionality that gets added by selecting SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it and that code isn't valid for Bolton that uses the old GPIO 100 interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11mb/google/zork/vilboz: Update register parameters for sx9324 tuningFrank Wu
To update the sx9324 registers after RF team fine-tuned the parameters. BUG=b:172397658 BRANCH=firmware-zork-13434.B TEST=build coreboot and verify the sx9324 function Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ief85bc61952144a1d7a151100d89938517078ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51936 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11spd.h: Move `DIMMx` macros to i440bx/raminit.hAngel Pons
These macros aren't needed anywhere else, so reduce their visibility. Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52061 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-11sb/intel/x/smbus.c: Correct register access widthAngel Pons
The register is 16 bits wide. Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10mb/prodrive/hermes: Fix eeprom readingArthur Heymans
The logic for bytes to copy to the function input pointer was wrong. What it did was to loop over all 2 bytes that need to be read and only copy the first byte. Change-Id: Ic08cf01d800babd4a9176dfb2337411b789040f3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-10mb/intel/shadowmountain: Enable Bluetooth config in the devicetreeSridhar Siricilla
The patch enables Bluetooth config in the devicetree and removes non-existent Bluetooth PCI interface. TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in the lsusb ouput. Output of lsusb: Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub Bus 003 Device 005: ID 8087:0033 Intel Corp. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/amd/cezanne: Set Power state after power failureKarthikeyan Ramasubramanian
Configure the power state to return to when the power is re-applied after power failure. BUG=b:183739671 TEST=Build and Boot to OS in Majolica and Guybrush. By default when the power fails the device turns on after power is re-applied. When the POWER_ON_AFTER_POWER_FAILURE is disabled, the device remains off even after the power is re-applied. Change-Id: I21c5da08c82156d6239450ef6921771da74cbaa1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52049 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/amd/common: Handle power resume after power failureKarthikeyan Ramasubramanian
Introduce a power management library to handle the power resume after power failure. Enable HAVE_POWER_STATE_AFTER_FAILURE config when this library is enabled. BUG=b:183739671 TEST=Build Guybrush and Majolica mainboard. Change-Id: Iea4ea57d747425fe6714d40ba6e60f2447febf28 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10soc/amd/cezanne: Add GRXS and GTXS methodEric Lai
Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-10mb/google/brya: Change GPP_E16 default to highAlex Levin
To enable WWAN we want to release it from reset start. BUG=b:180166408 TEST=WWAN enumerates on brya Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52199 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10soc/intel/alderlake: Drop unreferenced `InternalGfx`Angel Pons
This option is not referenced anywhere. Drop it. Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52104 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10cpu/intel/haswell: Use new fixed BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5fb31f88bbf7c2f1e44924ca2d3169257a9598dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10mb/dell/optiplex_9010: Use new fixed BAR accessorsAngel Pons
Change-Id: I4d949d252ca24ebd4e4ed9c7dd17ede3810a8bfd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-10nb/intel/i945: Use new fixed BAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: Ifea441ad95293ad93d11a5f2521370cfd387289b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-20 10:15:10 +0000