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2018-10-18minnowmax: allow both 1333 and 1066 MHz memory SKUsMichał Żygowski
The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. Use frequency as a proxy to determine SKU. The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the E3827 and E3845 are 1750MHz and 1910MHz, respectively. This will allow to boot quad-core Minnowboard Turbot especially. Change-Id: I5e57dd419b443dfa742c8812cec87274af557728 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27989 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18tpm/tspi: clean up tpm_setup function flowJoel Kitching
Introduce two helper functions for more readable code. Use epilogue function instead of goto for error handling. BUG=None TEST=None Change-Id: Ibea44880683a301e82ee2ba049003c36fcb44eba Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/29026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-18cpu/x86/smm: Fix non-local header treated as localElyes HAOUAS
Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18src/{sb/intel,mb/google/auron}: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-18ec/google/chromeec: Use common MEC interfaceDuncan Laurie
Switch to using the common MEC interface instead of the Chrome EC specific code. Tested on a Chell chromebook that has a MEC based Chrome EC to ensure that the EC interface is still functional. Change-Id: Idf26e62c2843993c2df2ab8ef157b263a71a97c9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18ec/google/common: Add a common MEC interfaceDuncan Laurie
In order to re-use the MEC interface code in the Chrome EC driver move it to a common directory within the ec/google directory. The Chrome EC driver itself is changed to use this interface in the next commit, and future commits will introduce a new EC that also uses this interface. Change-Id: I13516b5e4c4c49f53bb998366284a26703142e2a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18mediatek/mt8183: Add EMI init for DDR driver initHuayang Duan
Add EMI config to initialize memory. BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea Reviewed-on: https://review.coreboot.org/28835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18mediatek/mt8183: Add register definitions of DRAM controllerTristan Shieh
Add register definitions of DRAM controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I8b51486deab856a783b87f0b2812a991d4111020 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-18mb: Fix non-local header treated as localElyes HAOUAS
Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18mb: Replace MSR addresses with macrosElyes HAOUAS
Change-Id: I020431ba8eb61f5ce256088b919c049985331d64 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOSJulius Werner
CB:26053 changed coreboot's default loglevel from SPEW to DEBUG. This may be the most reasonable choice for most users that are mostly interested in the UART console. However, on Chrome OS devices the UART is disabled for production configurations anyway, and instead they rely heavily on the CBMEM console for remote debugging and bug reports. For these kinds of cases more info is almost always better, and you can't easily reproduce a remotely filed bug if you notice that you need some info that is only provided by BIOS_SPEW. On the other hand, the cost of logging extra info to the CBMEM console is pretty negligible. Therefore, let's bump the loglevel for CONFIG_CHROMEOS in particular back up to the maximum. (Unfortunately, it seems that you can't 'select' a choice option from another option, so this has to go in the console/Kconfig file.) Change-Id: I50724e3f7f8f57fdbc5846f21babc71798b21b65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/29144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40Richard Spiegel
Register 0x40 of miscellaneous MMIO is double defined, with different names, which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO registers. BUG=b:117818431 TEST=Build grunt. Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove double defined SPI100_SPEED_CONFIGRichard Spiegel
SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the first definition are unused. Remove first definition and its associated bits and shifts. BUG=b:117818430 TEST=Build grunt. Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-18soc/amd/stoneyridge: Remove double definition for wideioRichard Spiegel
WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the definitions within MMIO definitions, as wideio is not related to MMIO. BUG=b:117814228 TEST=Build grunt. Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove DEV_D18F4 definitionRichard Spiegel
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is the same as SOC_PM_DEV. Remove the definition, and replace its use in tsc_freq.c with SOC_PM_DEV. BUG=b:117754424 TEST=Build and boot grunt. Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge: Remove double defined GPIO MMIO basesRichard Spiegel
GPIO control a mux base addresses are defined within MMIO definitions and again bellow as GPIO specific base addresses. Eliminate those outside MMIO bases. Rename them to something indicating that they are both MMIO and related to GPIO. BUG=b:117754420 TEST=Build grunt. Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29156 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18amd/stoneyridge/include/soc: Re-arrange NB IOAPIC definitionsRichard Spiegel
There's no indication that they are accessed through D0F0. Add a D0F0 header and move IOAPIC definitions under it. The registers defined to be accessed through index/data pair should be indented relative to the index/data pair definition. BUG=b:117754786 TEST=Build grunt. Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29155 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge/smi.c: Prefer using '"%s...", __func__'Richard Spiegel
In function smm_setup_structures(), the function name is used in a print string. Use __func__ instead. BUG=b:117642170 TEST=Build grunt. Change-Id: Icac5ea997289ef75fb246a09715cbca4442a57f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29154 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge/southbridge.c: Change comparison orderRichard Spiegel
Comparison should place the constant on the right side. Southbridge.c has 6 instances where the opposite happens. Reverse the order of six comparisons to eliminate checkpatch warnings: WARNING: Comparisons should place the constant on the right side of the test BUG=b:117656929 TEST=Build grunt. Change-Id: I94f17b81f845fa94599f93c0be1144ffcb8e4165 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29153 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18soc/amd/stoneyridge: Remove "else" after a returnRichard Spiegel
File smbus_spd.c has 2 instances of if()/else where the if tests for an error condition and returns just before the "else" statement. These "else" statements are not needed. BUG=b:117648025 TEST=Build and boot grunt. Change-Id: Ie8298773ae455dbb1125420ec65df24f3c65eb44 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18drivers/intel/fsp*: Use newly added post codes for memory param prepFurquan Shaikh
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to search from where these post codes are generated during boot flow. Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init to make it consistent with fsp1_1 memory init. Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18console/post_codes: Add post codes for memory param prep callbackFurquan Shaikh
This change adds two new post codes to indicate start and end of memory param preparation in callbacks to SoC/mainboard code: 1. 0x34: Start of memory preparation 2. 0x36: End of memory preparation These post codes are already used in coreboot. This change just ensures that the codes are defined in post_codes.h for easy lookup. These post codes are useful if SoC/mainboard decides to do a reset of the platform before returning back to memory initialization. Change-Id: I065518caedb7943d960a8a5c8708823b8eb3246d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-18intel/common/block: Fix issue found by klockworkJohn Zhao
src/soc/intel/common/block/pmc/pmclib.c Function acpi_get_sleep_type: Pointer ps checked for NULL may be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I15fe39fd9f930be56d03c2ffe62fb6f17249d4b5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-18mb/lenovo/*/romstage: Use macros instead of magic numbersPeter Lemenkov
Apparently coreboot still uses magic numbers instead of macros in some Lenovo mainboards. Let's use macros instead. Also removed FDD from l520 romstage (original value, 0x3c0c, means that FDD_LPC_EN was also enabled). Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/28976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-18soc/intel/skylake: Prevent disabling of TCONaresh G Solanki
In Skylake/Kabylake, if ACPI PM timer is disabled then TCO also gets disabled & vice versa. FSP default config for EnableTcoTimer is disabled, this caused ACPI PM timer & TCO to be disabled by FSP even when config PmTimerDisable = 0. Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config PmTimerDisable. BUG=None TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused reboot after running shell command: cat >> /dev/watchdog0 Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/29108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-10-18mb/lenovo/z61t: Add VBT-filePeter Lemenkov
This file was extracted directly from the vendor's firmware ver. 2.27. Change-Id: Ic2d2b259f3b535a791c9dcfdf962c03a0bab87a2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-17soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake RVP8 platforms. - Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB, SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device. - Add new device IDs to intel common code respectively. - Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8. - CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c is modified accordingly. - Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8. BUG=None TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices are enumerated and cross checked devices ids in serial logs and UEFI shell. Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28718 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8praveen hodagatta pranesh
- Add new mainboard variant coffee lake RVP8, which is CRB for coffee lake-s processor, support U-DIMM DDR4 memory module. - Modify cfl_h devicetree to enable IO devices, configure PCIE root port clock source, usb over current pin as per board schematics. - Select cannonlake PCH-H chipset config for both cfl_h & cfl_s. - Add GPIO table as per board schematics. BUG= None TEST= Build and flash, confirm boot into yocoto & windows OS on both cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA, display, power functionalities. Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/29066 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mb/lenovo/*/acpi: Store the requested state wake state for bluetooth and WWANPatrick Rudolph
L520 and T420 should also use it - platforms are very similar to t420s and t530. Z61t is based on T60/X60, X131e is based on X230 so commit with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be applied as well. All four platforms are using ec/lenovo/h8 embedded controller. Change-Id: Ib177f024871e82979dd430da86f1551aef14d446 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17google/kukui: Configure USBTristan Shieh
Set up USB host controller. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-10-17mediatek/mt8183: Add USB supportJumin Li
This patch implements SoC-specific defines of mt8183 and links the common code to support USB. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1224cf24f92b07f3c1814f1cbfef96aafa5a992b Signed-off-by: Jumin Li <jumin.li@mediatek.com> Reviewed-on: https://review.coreboot.org/28787 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mediatek: Refactor USB code among similar SoCsTristan Shieh
Refactor USB code which will be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I06fefb4149a489be991e13ddf624082d11e31765 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-17vboot: do not extend PCRs on resume from S3Joel Kitching
BUG=b:114018226,chromium:873099 TEST=compile coreboot Change-Id: I6840c45604535089fa8410f03c69702bec91218f Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17tpm/tpm_setup: fail on invalid result from tlcl_resumeJoel Kitching
BUG=b:114018226 TEST=compile coreboot Change-Id: I8f5df2b0119d35e4000fe62bf1bba6ca07f925f3 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17soc/cavium/cn81xx: Drop dead do_soft_reset() implementationNico Huber
Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-17arch/x86/exception: Improve the readability of a commentJonathan Neuschäfer
Add punctuation and fix a typo. Change-Id: Ic61c665f7e2daefb50b478a1710ea66c8a88235a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-17mb/lenovo/t530: Fix double indentation in Kconfig.nameJonathan Neuschäfer
There is no need to indent these lines with two tabs. Change-Id: I2164f4e3ea48db8dc5242a55b0452782dae19a4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-17mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer
The assignment of header->checksum was in some cases done twice, or unnecessarily split into two lines. Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-10-17mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10Roy Mingi Park
While these pins were set to a pull-down 20KOhm, NPCX EC consumes ~2.1mW higher power. Becasue there was leakage current on both GPIO67 and GPIO70 from NPCX EC. With the external pull-up 10KOhm for USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current. BUG=b:117139495 TEST=Check nxpc EC power to see power improvement Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/29007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17drivers/intel/fsp2_0: Add new config option to support FSP CARpraveen hodagatta pranesh
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU microcode length and base address in CBFS to FSPT binary as init parameters. Add new config FSP_T_XIP in Kconfig, which is selected by platform config. If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS so that it can be executed in place. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup. Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17mb/google/poppy/variants/nocturne: Tune DPTF settings for CPUSumeet R Pawnikar
Update CPU passive temperature threshold value from 70C to 80C, to avoid early throttling for spiky workloads. Also, change CPU throttling interval from 1 sec to 5 sec for CPU temperature. BUG=b:116400298 BRANCH=None TEST=Manual performance testing on nocturne. Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/29044 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-16mb/*/*/Makefile.inc: Remove acpi_tables.c from MakefilesPeter Lemenkov
It always included if ACPI is supported since commit 822bc65 with Change-Id I372dbd03101030c904dab153552a1291f3b63518 ("ACPI: Remove CONFIG_GENERATE_ACPI_TABLES"). Change-Id: If17a6f43e368ccf850031b349714fa1ec4d02c1d Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/28954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-15mb/google/poppy/variants/nami: Disable rear camera/DMIC for SyndraAmanda Huang
Since there are two cameras on Nami and only one camera on Syndra. We need to disable rear camera/DMIC on all Syndra sku. BUG=b:112876867 Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-15mb/lenovo/*/smihandler: Remove some unused includesPeter Lemenkov
Tried to build all affected mainboards - still compiles fine. Change-Id: I385cac1a75cee13453b831bd75b3ecc7a6d229fa Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-15mb/lenovo/*/dsdt: Remove HAVE_LCD_SCREENPeter Lemenkov
This define is no longer used by anyone. It was removed everywhere else with commit with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757. It seems that these two files were simply mislooked. So let's remove it. Change-Id: Ifbb62441e16e97c0cae0713968844e296619a880 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-15mb/asus/p5q_pro: Add mainboardArthur Heymans
This mainboard is quite similar to the p5qc. The main differences being a second PEG slot, the IDE slot and being DDR2 only. The following was tested: - both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the black slot) - USB - Ethernet NIC - PS2 Keyboard - COM1 - S3 resume Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/29102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15drivers/net/atl1e: Add driverArthur Heymans
A shortcoming of this driver is that if multiple devices with the same PCI ID are present and don't have an eeprom, they would all get the same macadress set. The r8168 driver deals with such cases so it should be easy to implement if needed. Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-10-15mb/asus/p5qc: Add mainboardArthur Heymans
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards. Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress) - S3 resume Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR3 fails because the proper clock signal does not get enabled. Even when fixing this it fails later or during memtest, so it should be considered unsupported for now Untested: - PCIe x1 ports (expected to work) - sound (expected to work) TODO: add documentation Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 02:34:58 +0000