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2016-12-18ACPI S3: Signal successful bootKyösti Mälkki
Just before jumping to OS wakeup vector do the same tasks to signal coreboot completion that would be done before entry to payload on normal boot path. Change-Id: I7514c498f40f2d93a4e83a232ef4665f5c21f062 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17794 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-18riscv: Add support for timer interruptsRonald G. Minnich
RISCV requires that timer interrupts be handled in machine mode and delegated as necessary. Also you can only reset the timer interrupt by writing to mtimecmp. Further, you must write a number > mtime, not just != mtime. This rather clumsy situation requires that we write some value into the future into mtimecmp lest we never be able to leave machine mode as the interrupt either is not cleared or instantly reoccurs. This current code is tested and works for harvey (Plan 9) timer interrupts. Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17807 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-12-17Revert "arch/x86/smbios: Correct manufacturer ID"Nico Huber
This reverts commit c86da67436827c25919a2f5966049485a58fc984. Alas, I have to disagree with this in every single line. The comment added to the top of the file only applies to a single function therein which sits over a hundred lines below. That's not much helpful. More- over, the link in the comment is already down ofc. The comment is also irritating as it doesn't state in which way (enco- ding!) it applies to the code, which presumably led to the wrong in- terpretation of the IDs. At last, if anything should have changed it is the strings, the IDs are resolved to. `smbios_fill_dimm_manufacturer_from_id()` has to resolve the IDs it gets actually fed and not a random selection from any spec. Since I digged into it, here's why the numbers are correct: The func- tion started with the SPD encoding of DDR3 in mind. There, the lower byte is the number of a "bank" of IDs with an odd-parity in the upper most bit. The upper byte is the ID within the bank. The "correction" was to clear the parity bit for naught. The function was later exten- ded with IDs in the DDR2-SPD encoding (which is actually 64-bit not 16). There, a byte, starting from the lowest, is either an ID below 127 plus odd-parity, or 127 which means look in the next byte/bank. Unused bytes seem to be filled with 0xff, I guess from the 0xff2c. Change-Id: Icdb48e4f2c102f619fbdca856e938e85135cfb18 Reviewed-on: https://review.coreboot.org/17873 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-17nb/x4x: Add other Eaglelake IGD PCI DID to listArthur Heymans
Currently only there is only one eaglelake board in coreboot (ga-g41m-es2l) featuring a G41 variant northbridge. Adding boards with a different variant (Q43, Q45, G43, G45, B43) will require this change for graphic initialisation. Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17900 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-17google/reef: Use exported GPIOs and ACPI regulator for touchscreenFurquan Shaikh
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-17drivers/regulator: Add driver for handling GPIO-based fixed regulatorFurquan Shaikh
This change adds the required device node in SSDT for defining GPIO-based fixed voltage regulator. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that ELAN touchscreen works with exported GPIOs and ACPI regulator. Change-Id: I4380aea0929fb7e81dbe83f940e3e51e983819f9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16google/eve: Set throttle offset to 10 degreesDuncan Laurie
Set the thermal throttle (prochot) activation to be 10 degrees below TJmax so PROCHOT# kicks in at 90C instead of 100C. BUG=chrome-os-partner:58666 TEST=boot on eve, check msr value before and after resume: > iotools rdmsr 1 0x1a2 0x000000000a6400e6 > echo mem > /sys/power/state > iotools rdmsr 1 0x1a2 0x000000000a6400e6 Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17901 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-16amd/gardenia: Enable LPC decodesMarshall Dawson
Turn on LPC decoding in romstage. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc) Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17227 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Enable HD AudioMarshall Dawson
Add ALC286 commands and update the PLATFORM_CONFIGURATION structure with the list address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee) Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17226 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Update PCIe and DDI lanesMarshall Dawson
Change the Carrizo settings used for Bettong to ones specific to Stoney on Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb) Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17225 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Enable SATA controllerMarshall Dawson
Duplicate the code from DB-FT3lc and use the correct names. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c) Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17224 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Update xHCI configurationMarshall Dawson
Remove a duplicated check and setting for xHCI during the AMD_INIT_RESET callout. This is handled by the wrapper. Also remove nearby commented code. EcChannel0 is not a member of FCH_RESET_DATA_BLOCK. Leave the check in AMD_INIT_ENV. Although AGESA honors what was previously requested, additional settings depend on the state of Usb.Xhci0Enable. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd) Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17223 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Configure GPIO signalsMarshall Dawson
Change the default configuration for the following settings: AGPIO14: BT radio disable AGPIO64: NFC PU AGPIO65: NFC wake AGPIO66: Webcam AGPIO69: PCIe presence detect AGPIO70: GPS sleep AGPIO116: MUX for Power Express Eval EGPIO119: SD power Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4) Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17222 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Remove board ID capabilityMarshall Dawson
Remove the last bit of Bettong board_id checking from Gardenia. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c) Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17221 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Remove rev-specific storage setupMarshall Dawson
Gardenia doesn't have the ability to modify settings depending on the board ID. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89) Change-Id: I2c928431306c669735cf735042855e95721bb107 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17220 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16amd/gardenia: Correct SPD AGESA calloutMarshall Dawson
Gardenia makes no special considerations for a board_id regarding SPD access and addressing. Remove this from the source and use the standard AGESA call. Make SPD address changes to devicetree.cb. Note that Gardenia is designed to be a two channel, single DIMM/channel system (some SKUs with two DIMMs on the second channel). However, this port is for the Stoney processor which is a single channel. As a result, the second DIMM slot is not usable. A future improvement could involve a port using a different processor, with unique devicetree files for each. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15) Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17219 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16mainboard/amd: Copy bettong to gardenia and update for buildMarc Jones
Use bettong as the reference for the gardenia mainboard. Update makefiles etc so it builds. This patch intentionlly keeps the carrizo_fch.asl file to remain synchronized with the AMD PI package. Remove items that do not apply to the Stoney APU, rewrite the comments associated with the PCIe devices, and fix up the SPD register association to match the 00670F00 chip.h. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e) Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17218 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16drivers/pc80/tpm: Set default TPM acpi path if unsetPhilipp Deppenwiese
Enable default acpi path PCI0.LPCB if TPM support is selected in the kconfig system and the acpi path is not set via acpi_name callback in the platform code. Thanks to Aaron Durbin for providing this fix. Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/17855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16nb/intel/sandybridge/raminit: Separate Sandybridge and IvybridgePatrick Rudolph
Add custom files for Sandybridge and IvyBridge functions. Move only the minimal required functions into separate files. Both files' functions are going to call raminit_common functions. No functionality is changed. Sandybridge code path tested on Lenovo T420. Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17605 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16mb/intel/kblrvp: Increase preram cbmem console sizeNaresh G Solanki
Some part of preram cbmem console output is truncated. Increase preram cbmem console size to 0xd00 to avoid the same. Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-16x86: Configure premem cbmem console sizeNaresh G Solanki
Sometime preram cbmem logs are truncated due to lack of space (default preram cbmem console size is 0xc00). Provide Kconfig option to configure preram cbmem console size so that mainboard can configure it to required value. Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-16Set the fsb timer correctly for Netburst CPUsArthur Heymans
On Netburst (Pentium 4) the fsb cannot be read from MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead. Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17832 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-12-16drivers/i2c/generic: Allow mainboards to export reset and enable GPIOsFurquan Shaikh
Add power management type config option that allows mainboards to either: 1. Define a power resource that uses the reset and enable gpios to power on and off the device using _ON and _OFF methods, or 2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can directly toggle the GPIOs as required. GPIO type needs to be updated in drivers_i2c_generic_config to use acpi_gpio type so that it can be used for both the above cases. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that elan touchscreen works fine on reef using exported GPIOs. Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17797 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16acpi_device: Add special HID for DT namespaceFurquan Shaikh
BUG=chrome-os-partner:60194 BRANCH=None TEST=Compiles successfully Change-Id: I0fe146cf2235c7c4ad3ea5589ed556884de3a368 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16google/eve: Enable touch devicesDuncan Laurie
Enable the actual touch devices to be probed by the kernel and remove the placeholder devices that I put in before and were used for initial bringup. BUG=chrome-os-partner:58666 TEST=tested on eve Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16tpm2: handle failures more gracefullyVadim Bendebury
When trying to bring up a device with a malfunctioning TPM2 chip, the driver currently gets stuck waiting for SPI flow control, causing bricked devices. This patch puts a 100 ms cap on the waiting time - this should be enough even for a longest NVRAM save operation which could be under way on the TPM device. BRANCH=gru BUG=chrome-os-partner:59807 TEST=with a matching change in depthcharge, now a gru with corrupted SPI TPM comes up to the recovery screen (it was not showing signs of life before this change). Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/17898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-16samsung/exynos5420: Fix test for src < 0Patrick Georgi
It was unsigned, not a good place to be for testing < 0. Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1241911 Reviewed-on: https://review.coreboot.org/17888 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-16mediatek/mt8173: Check the right set of bits in USB controllerPatrick Georgi
Change-Id: Ic1d1b85a1d7e85b555a93b3a0b55fe310b26e34a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1353362 Reviewed-on: https://review.coreboot.org/17875 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16google/eve: Enable native mode for UART pins in bootblockDuncan Laurie
Put the UART pins into native mode in bootblock so they are not floating when we try to communicate with H1 over I2C. Without a serial console enabled BIOS these pins were not configured until ramstage. BUG=chrome-os-partner:60935 TEST=Boot Eve board without serial console and H1 TPM enabled Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-16drivers/i2c/hid: Add generic I2C HID driverDuncan Laurie
Add a generic I2C-HID driver for these types of devices that do not need extra functionality. This allows a new device to be added without having to write a new driver. The i2c-hid PNP0C50 is automatically added as the _CID for the device in the ACPI Device. BUG=chrome-os-partner:58666 TEST=used on eve to describe a new i2c-hid touch controller Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-15mb/roda/rv11: Add new boards Lizard RV11 and RW11Dennis Wassenberg
The Roda Lizard RV11 is a comparatively lightweight, full-rugged notebook. It's based on a 17W TDP dual core Ivy Bridge CPU. The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o options). The RV11 is the first board to use the native graphics initialization by libgfxinit. Tested so far, are the internal eDP port, DP and VGA. Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17446 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15mb/ga-945gcm-s2l: Fix resume from suspendArthur Heymans
Checking for memory self refresh can generate false positives, as explained in faa6beb: "northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option". This seems to be the case for this motherboard. TESTED on ga-945gcm-s2l. Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17617 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-15smbios.h: add missing SKU field to type3 tableMatt DeVillier
The type3 SMBIOS table has a non-optional SKU field at the end, which causes a parsing error when missing. Add but do not populate it. Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17851 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-15ec/ene932: correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString() where needed Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17783 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-15mainboard/google/reef: clear normal MRC cache on recovery retrainAaron Durbin
For Chrome OS the normal MRC cache should be cleared when a hardware retrain recovery request is observed. The reason is that since there are 2 different MRC cache slots there needs to be a mechanism which allows an end user make a system bootable again if the MRC settings happen to not allow the system to boot any longer. Therefore, one just needs to enter recovery with the hardware retrain flag and the system normal MRC cache slot will be invalidated. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17871 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15soc/intel/common: provide option to invalide MRC cache on recoveryAaron Durbin
Allow a board/platform to invalidate the normal MRC cache when hardware retraining is requested in recovery mode. A small 4 byte payload is used to update the latest data written. It will of course fail on MRC cache retreival on next usage. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17870 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15ec/google/chromeec: query cbmem for retrain statusAaron Durbin
The EC switches, including the hardware retrain flag, are cleared when handing off the vboot state in romstage. However, one may still want to query the state of the hardware retrain flag. Thus, add a method to get the flag from cbmem. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17869 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15lib/cbmem: allow anyone to use cbmem_possibly_online()Aaron Durbin
The cbmem_possibly_online() is a helpful construct. Therefore, push it into cbmem.h so other users can take advantage of it. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17868 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15soc/intel/apollolake: don't probe flash manuallyAaron Durbin
Rely on boot_device_spi_flash() to provide the spi_flash object. There's no need to duplicate the probing logic. BUG=chrome-os-partner:56151 BRANCH=reef Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17867 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15google/reef: Remove VARIANT_DIR definitionMartin Roth
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be defined in each mainboard. Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17841 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15drivers/i2c: Pass in i2c_generic_config into i2c_generic_fill_ssdtFurquan Shaikh
Remove any assumptions required for the drivers using i2c_generic to have drivers_i2c_generic_config structure at the start of the driver config. Instead pass in a pointer to drivers_i2c_generic_config from the calling driver. Change-Id: I51dc4cad1c1f246b51891abf7115a7120e87b098 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17857 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-15ec/chromeec: Correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString(). Change-Id: I4fdbf97e9b75030374dffc99a954dd9faa6a5209 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15pcf8523: Fix wrong initialization of several registersWerner Zeh
In the case where the RTC is initialized after the battery is completely drained the bits for power_mode and cof_selection are set up with wrongly applied masks. In the case where the RTC is re-initialized again with no power-loss after the last initialization the bits for cap_sel, power_mode and cof_selection are not shifted to the right position. Both errors lead to a wrong initialization of the RTC and in turn to a way larger current consumption (instead of 120 nA the RTC current rises to over 2 µA). This patch fixes both errors and the current consumption is in the right range again. TEST=booted mc_bdx1 and verified current consumption of RTC Change-Id: I8594f6ac121a175844393952db2169dbc5cbd2b2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17829 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14lib/spd_bin: Check return code & remove dead codeNaresh G Solanki
Remove dead code to address CID 1366756 Control flow issues (DEADCODE) Add return value check to address CID 1366755 Error handling issues (CHECKED_RETURN) Found-by: Coverity Scan #1366755 Found-by: Coverity Scan #1366756 Change-Id: Id02f6915ec7c6a4abfce20332c55833683e52d77 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17838 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-14vendorcode/amd: drop dead codePatrick Georgi
Change-Id: Ie67e1f7887e8df497d7dfd956badd9e06fd5d8a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1254651 Reviewed-on: https://review.coreboot.org/17833 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-14vendorcode/amd: Fix non-terminating loopPatrick Georgi
Code is copied from agesa/common's amdlib.c. Things can probably be deduplicated. Change-Id: I9c8adab5db7e9fd41aecc522136dfa705c1e2ee6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229662 Reviewed-on: https://review.coreboot.org/17834 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins)
2016-12-14soc/intel/broadwell/lpc.c: don't zeroize existing gnvs tableMatt DeVillier
The gnvs table only needs to be zeroized after init; zeroizing an existing/populated table renders all I2C devices completely non-functional. TEST: boot Linux and observe all I2C devices functional Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17828 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-14google/eve: Configure I2C3 pins as GPIO inputsDuncan Laurie
On this board i2c3 bus is connected to the display TCON, but it is acting as the master when it has power so it can read from its own EEPROM on the bus. In order to prevent any possible issues in S0 make these pins input on the SOC. BUG=chrome-os-partner:58666 TEST=tested on eve board, but this bus was not used before so there is no visible change in behavior. Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17800 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13sio/ite/it8783ef: Return (0) in ACPI _PSC methodsNico Huber
Current ACPI code for UARTs uses the PNP_DEFAULT_PSC macro for _PSC (current power state) methods. Override it to `Return (0)` (i.e. cur- rent state is D0) as the IT8783E/F doesn't have power management. Change-Id: I3c858dde287dbf7e5fc0c20abb1fd374887acdde Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17791 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-12 12:15:37 +0000