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2017-11-21spi/tpm: claim locality just once during bootVadim Bendebury
All coreboot stages using TPM start with the same sequence: check if locality is claimed, if so, release it by writing 'active locality' bit, then try claiming it. This is actually not a proper procedure: section "5.5.2.3.1 Command Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification Level 00 Revision 00.430 Family 2" lists overwriting active locality status bit as a means of triggering TPM command abort. On top of that, none of the coreboot stages releases locality, it is enough to claim it once when device starts booting. In fact, locality being active when the device is in verstage is most likely due to delayed TPM reset processing by the Cr50 TPM: reset is an asynchronous event, and is processed once current command processing completes. The proper procedure is to wait if locality is active until it is released (which will happen when Cr50 processes reset) and then proceed to claim it. This needs to happen only during verstage, other stages using TPM are guaranteed has been claimed earlier. BRANCH=gru BUG=b:65867313 TEST=the new autotest triggering EC reset during key generation process does not cause boot failures on Fizz device any more. Below are times verstage had to wait: TPM ready after 3132 ms TPM ready after 22120 ms TPM ready after 4936 ms TPM ready after 6445 ms TPM ready after 11798 ms TPM ready after 27421 ms TPM ready after 4582 ms TPM ready after 7532 ms TPM ready after 27920 ms TPM ready after 3539 ms TPM ready after 12557 ms TPM ready after 6773 ms TPM ready after 1631 ms TPM ready after 197 ms TPM ready after 24330 ms TPM ready after 3241 ms Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-21src/soc/intel/apollolake: move TCO1 disable into bootblockVadim Bendebury
Cr50 reset processing could take long time, up to 30 s in the worst case. The TCO watchdog needs to be disabled before Cr50 driver starts, let's disable it in bootblock. BRANCH=none BUG=b:65867313, b:68729265 TEST=verified that resetting the device while keys are being generated by the TPM does not cause falling into recovery. Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21arch/x86: Write ACPI DBG2 table only if the device has been enabledMario Scheithauer
The commit 93bbd41e (soc/intel: Enable ACPI DBG2 table generation) causes a crash on the mainboard mc_apl1. On this mainboard all internal SOC UARTs in the devicetree are switched off. As a result, no resources are allocated to the UARTs. The function find_resource() expects an existing resource. Otherwise, the CPU will stop. It should therefore not only be queried whether a device is present, but also whether it is enabled. Change-Id: I56ce44ae0cf77916fcb640f79fb8944fe33177cd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-21vendorcode/amd/pi/00670F00: Clean up makefileMartin Roth
- Remove unnecessary cflags, exports, and variables - Don't include AGESA cflags in the entire build - Reformat build target BUG=b:69220826 TEST=Build Change-Id: I60cb20a3849439cb808f5d3919588853e9c8c734 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21soc/amd/stoneyridge: Add ELOG to SMMJohn E. Kabat Jr
1. Add ELOG entries to smihandler.c 2. Add save_state utilities that are needed by southbridge_smi_gsmi BUG=b:65485690 Change-Id: I458babe1694f042215dd0e1c3277856e340de86f Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21amd/stoneyridge/spi: Fix reads greater than 5 bytesMarshall Dawson
This corrects a bug in 918c8717 "amd/stoneyridge: Add SPI controller driver". Pass a pointer to din to the do_command() function so the caller's copy is correctly updated. The bug allowed reads <= 5 bytes to work correctly (3 bytes consumed in the FIFO by the address) but overwrote data in the din buffer on larger transfers. Change-Id: I32b7752f047112849871cafc9ae33c5ea1466ee1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21soc/amd/common: Remove duplicated #include amd_pci_int_defs.hRichard Spiegel
Remove <#include amd_pci_int_defs.h> from amd_pci_util.h, as the user of the functions declared in amd_pci_util.h don't need the contents of amd_pci_int_defs.h. BUG=b:62200907 Change-Id: I258d549d3eea3fb8919c0cddbb41dc2bc4738c4e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21mb/google: Update/add ChromeOS device marketing namesMatt DeVillier
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added marketing names for many ChromeOS devices; add some that were left out, correct some errors, and try to format model names/numbers consistently (or as consistently as the manufacturers allow). Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20mainboard/google/fizz: Enable separate MRC cache for recovery modeShelley Chen
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:69473883 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-20google/gru: Add config for scarlet-derived boardsEge Mihmanli
There is merit in having new boards use the pinouts and controls in scarlet. This adds a config so new scarlet-derived boards can easily use scarlet structure without going through every file and adding new logic. TEST=Run "emerge-scarlet coreboot" Signed-off-by: egemih@chromium.org Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3 Reviewed-on: https://review.coreboot.org/22517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-20soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao
Two W/A had been added here for EMMC to make it working properly. 1. Enable power gating after D3 entry, disable power gating before D0 entry. 2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of D3. BUG=b:69323943 TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform. Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19include/timer.h: add NSECS_PER_SEC macroLin Huang
Change-Id: I4367f84be5a4bd635b422b6e7cbdc9aa3ccfbf5c Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove dependency on amd/include dirMartin Roth
Copy the two headers used by the Stoney BinaryPI implementation into the 00670F00 directory so that any changes that are made to them don't affect other platforms. BUG=b:67299330 TEST=Build Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mb/google/kahlee: Move ec.h into variant include directoriesMartin Roth
The mainboard directory is included through the PI makefile - most mainboard directories aren't in the include path at all. Move the ec.h file into the baseboard/variant directory that is already in the include path. BUG=b:69220826 TEST=Build Change-Id: I89d361b700c66ba576de724927574fdab9461fc6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove cpuFamilyTranslation.cMartin Roth
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into the build, so it's obviously not needed. BUG=b:69220826 TEST=Build Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Update memory.cMartin Roth
This fixes some issues with the initial implementation that was copied from reef. - The board ID value shouldn't be size_t - it's not a size. - Kahlee doesn't even need the memory.c file - it uses an SoDIMM. BUG=b:68293392 TEST=build stoney platforms, boot kahleebo Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22515 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-17Move amd/stoneyridge/include/amd_pci_int_defs.h to include/soc/Richard Spiegel
Move src/soc/amd/stoneyridge/include/amd_pci_int_defs.h to src/soc/amd/stoneyridge/include/soc/. After much discussion, src/soc/amd/stoneyridge/include/soc is probably the best location. It was found that there are other common code that include headers from this folder. BUG=b:62200907 Change-Id: I69e0a54e5d64ae28919871c687a0177786b789c8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17amd/gardenia: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21854 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17soc/intel/cannonlake: fix gpio pin numbersBora Guvendik
Update pin numbers to match kernel cannonlake pinctrl driver. TEST=boot to OS Change-Id: Id65736db03200fd434dd9292ce081727abd6832b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22477 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17soc/intel/cannonlake: Add cpu.asl fileShaunak Saha
This patch adds the cpu.asl file in cnl. We are only defining the PNOT method here in this patch as this is needed by the ec/google/chromeec/acpi/ec.asl file for the AC methods. TEST= code compiles and boots when we include the ec.asl file. Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-17amd/stoneyridge: Enable SMI trap on SlpTypMarshall Dawson
Program PMx08 to support SMIs when software writes the SlpTyp bit in the Pm1Control register. The southbridge needs to send the SMI message prior to the completion response of the I/O cycle. Also, disable sending the STPCLK message before the completion response. Disable the SlpTyp functionality, then enable the SMI source. BUG=b:65595850 Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Add SlpTyp SMI handlerMarshall Dawson
When an SMI occurs due to SlpType, interpret the type of request being made. If it's S3 or higher, flush the cache and disable further SMIs. Reenable SlpTyp functionality in the ACPI logic and reissue the cycle. BUG=b:65595850 Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Add SPI controller driverMarshall Dawson
Add more definitions for the controller registers and fields. Add source that is adapted from hudson and updated for Stoney Ridge. This was tested with follow-on patches that write S3 data to flash. BUG=b:68992021 Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17mb/lenovo/t400/blc.c: Add LTN154P2-L05 to whitelistKevin Keijzer
TESTED on Lenovo T500 Change-Id: I5546641cb34264e29ccb3398dd68f6144dafe524 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-17mb/lenovo/t400: Add LTN154X3-L02 to list of known displaysKevin Keijzer
TESTED on Lenovo T500 Change-Id: I9c9fef82ca4af99c7d4813e0ab0e315fde93b972 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22475 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-16vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.hMartin Roth
coreboot doesn't need AGESA's version of Filecode.h. Some of the files that have been copied from AGESA include the header, so we can't get rid of it completely yet. - Remove includes from files that weren't copied from the AGESA source. - Remove FILECODE definitions from coreboot source. BUG=B:69220826 TEST=Build Gardenia; Build & boot Kahlee. Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-16vendorcode/amd/pi: Create stoney version of amdlibMartin Roth
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and update the 00670F00 Makefile to use it instead of using the common version. This allows changes to stoney without affecting the rest of the AMD binary PI platforms. BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I2fe4303f882938e9d917a3001476213f49426455 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16vendorcode/amd/pi: Split stoney PI into its own MakefileMartin Roth
- Copy vendorcode/amd/pi makefile to 00670F00 directory - Remove all stoney references from the vendorcode/amd/pi makefile - Remove all non-stoney references from 00670F00 Makefile - Remove directories that don't exist from 00670F00 Makefile -- Proc/CPU/Feature -- Proc/Fch/Kern -- Proc/Fch/Kern/KernImc BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I34690cfc3b1c4508d25d7cf062fcb9aea5945634 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16drivers/spi/tpm: Poll TPM_VALID bit until validShelley Chen
In case the TPM is doing a long crypto operation the initial probe could be very delayed. Rather than end up in recovery make the delay long enough to accommodate the (current) long crypto times. This would add a maximum of 30 seconds to boot time. Mirroring changes done on i2c side in CL:756918 BUG=b:65867313, b:68729265 BRANCH=None TEST=Make sure fizz boots up Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15variants/kahlee: Add thermal ASLMarc Jones
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS thermal values in the mainboard finalize. BUG=b:67999819 Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15google/kahlee: Get power plug notification from the ECMarc Jones
Set the EC SCI reporting mask to include the power plug reporting. BUG=b:65637324 TEST=Check power_supply_info on AC/DC. Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to socRichard Spiegel
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-15soc/intel/skylake: Make use of common CSE code for skylakeSubrata Banik
TEST=Ensures global reset could able to reset system. Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15soc/intel/common: Use HOST_CSR to get circular Buffer DepthSubrata Banik
As per CSME BWG section 3.4.4. The Circular Buffer Depth can find by checking B0:D22:F0 MMIO_HOST_CSR register. TEST=Build and boot eve/soraka/reef/cnl-rvp Change-Id: I1d3c09077e040b5c32b3c8be867a07f392ea4e1c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15soc/intel/common: Add HECI message retry countSubrata Banik
Send/Receive HECI message with 5 retry count in order to avoid HECI message failure. TEST=Build and boot eve/soraka/reef/cnl-rvp Change-Id: I76662f8080fe312caa77c83d1660faeee0bdbe7e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22443 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15soc/intel: Enable ACPI DBG2 table generationDuncan Laurie
Enable the ACPI DBG2 table generation for Intel boards. This is a Microsoft defined ACPI extension that allows an OS to know what the debug port is on a system when it is not enabled by the firmware, so it does not show up in the coreboot tables and cannot be easily found by a payload. broadwell: Use byte access device, set up only when enabled since it relies on the port being put in byte access mode and using this serial port for debug was not standard in this generation. skylake: Enable for the configured debug port. Skylake uses intelblocks for UART but not ACPI. common: Enable for the configured debug port. This affects apollolake and cannonlake. Tested by compiling for apollolake/broadwell, tested by reading the DBG2 ACPI table on kabylake board and using IASL to dump: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/22453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15arch/x86/acpi: Add support for writing ACPI DBG2 tableDuncan Laurie
Add a function to create an ACPI DBG2 table, which is a Microsoft ACPI extension for providing a description of the available debug interface on a board. A convenience function is provided for creating a DBG2 table with a 16550 UART based on a PCI device. This is tested by generating a device and verifying it with iasl: [000h 0000 4] Signature : "DBG2" [004h 0004 4] Table Length : 00000061 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3B [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" [020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] Info Offset : 0000002C [028h 0040 4] Info Count : 00000001 [02Ch 0044 1] Revision : 00 [02Dh 0045 2] Length : 0035 [02Fh 0047 1] Register Count : 01 [030h 0048 2] Namepath Length : 000F [032h 0050 2] Namepath Offset : 0026 [034h 0052 2] OEM Data Length : 0000 [036h 0054 2] OEM Data Offset : 0000 [038h 0056 2] Port Type : 8000 [03Ah 0058 2] Port Subtype : 0000 [03Ch 0060 2] Reserved : 0000 [03Eh 0062 2] Base Address Offset : 0016 [040h 0064 2] Address Size Offset : 0022 [042h 0066 12] Base Address Register : [Generic Address Structure] [042h 0066 1] Space ID : 00 [SystemMemory] [043h 0067 1] Bit Width : 00 [044h 0068 1] Bit Offset : 00 [045h 0069 1] Encoded Access Width : 03 [DWord Access:32] [046h 0070 8] Address : 00000000FE034000 [04Eh 0078 4] Address Size : 00001000 [052h 0082 15] Namepath : "\_SB.PCI0.UAR2" Raw Table Data: Length 97 (0x61) 0000: 44 42 47 32 61 00 00 00 00 3B 43 4F 52 45 20 20 // DBG2a....;CORE 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE 0020: 00 00 00 00 2C 00 00 00 01 00 00 00 00 35 00 01 // ....,........5.. 0030: 0F 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00 // ..&............. 0040: 22 00 00 00 00 03 00 40 03 FE 00 00 00 00 00 10 // "......@........ 0050: 00 00 5C 5F 53 42 2E 50 43 49 30 2E 55 41 52 32 // ..\_SB.PCI0.UAR2 0060: 00 // . Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar
During S3 cycling, system entered S3 only once and falied to enter S3 the second time. The system gets stuck at this point and we have to do a cold reboot to restore the system. Since XHCI IP is able to power gate during kernel freeze/suspend, this patch removes unnecessary device gating from ASL. This helps in continuous cycling of S3. BUG=b:69115421 TEST=run powerd_dbus_suspend multiple times and check if the system enters and resumes from S3. Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15device: further untangle device_t from struct deviceAaron Durbin
This further allows compilation units to be re-used without having to add macro guards because of declarations not being around in the __SIMPLE_DEVICE__ case. These declarations are for functions that operate on struct device. struct device is a known type so just expose the functions using the correct type. Also, DEVTREE_CONST is empty while in ramstage so there's no reason to separate the declarations. Lastly, fix up device_util.c to use the proper types. It's only compiled in ramstage and it only operates on struct device. Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Add DSP calibration clock name/rate for RT5514Cheng-Yi Chiang
Add a property for DSP calibration clock name and rate such that RT5514 codec driver can control ssp1_mclk for DSP clock calibration. BUG=b:67763576 TEST=boot on eve check RT5514 codec driver can get this device property. Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31 Original-Reviewed-on: https://chromium-review.googlesource.com/756261 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Set DSP SPI clock to 12MHzDuncan Laurie
To enable faster download of hotword data set the SPI clock to the Realtek 5514 DSP chip to 12MHz instead of the default 1MHz. BUG=b:67763576, b:66161281 TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw Change-Id: I92710eae25613a8202c63888b86a269803c40fe6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9 Original-Reviewed-on: https://chromium-review.googlesource.com/686675 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Chinyue Chen <chinyue@chromium.org> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable VMXDuncan Laurie
This feature was enabled at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot. Since we want this enabled anyway just set it this way in the BIOS so it matches what the kernel expects. BUG=b:68666100 TEST=pass firmware_FWtries on Eve with R63 OS image Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/749733 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Tune I2C4 hold timesDuncan Laurie
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz. BUG=b:67029862 TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/739841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Enable AER and LTRFurquan Shaikh
AER and LTR must be enabled individually on ports that need it, in this case it should be enabled for WiFi and NVMe. BUG=b:65457528 TEST=Wifi team verified that the performance is better with these changes. Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/671211 Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Use rt5663 driver and set propertiesDuncan Laurie
Use the rt5663 driver and provide values for the offsets which are needed for providing manual values to compensate the DC offset for L and R channels between headphone and headset. BUG=b:62712227 TEST=build and boot on eve and ensure rt5663 is functional. Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425 Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/611606 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org> Reviewed-on: https://review.coreboot.org/22446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/google/eve: Remove ACPI control of touchscreen powerDuncan Laurie
Change the touchscreen power control back to coreboot instead of under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L pin back to an output. This reverts previous changes to touchscreen GPIOs that were made to get back to a known good/working state. Having ACPI control these pins was resulting in a small percentage of touchscreen not being discovered at boot. This platform is not intending to use S0ix so the ACPI control is not needed. BUG=b:63718744 TEST=manual testing on Eve devices. Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/572692 Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Commit-Queue: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/22445 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14mb/amd/gardenia: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia Change-Id: I3c9ae7a435fadabf577f1f65ad4a6aa6234e9a29 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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