summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-01-08mb/google/dedede: Enable "FastPkgCRampDisable" upd for noise mitigationMaulik V Vaghela
As part of acoustic noise mitigation calibration, we need to enable FastPkgCRampDisable upd along with slew rate = 1. This values has been derived based on noise calibration done. Please refer document 575216 for procedure. BUG=None BRANCH=dedede TEST=correct value has been programmed and slew rate measurement is correct on scope. Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-08soc/intel/jasperlake: Update acoustic noise related parametersMaulik V Vaghela
We need to fill Acoustic noise mitigation related UPDs only in case when acoustic noise mitigation is enabled. This will also clarify the user that they need to enable Acoustic noise mitigation while using this config in mainboard. We're only filling UPD for domain VR index 0 since there is only one VR domain for JSL (VCCIN VR). Reference: JSL EDS (Document# 613601) (Chapter 3.4) BUG=None BRANCH=dedede TEST=UPD values are getting filled correctly when Acoustic noise mitigation is enabled. Change-Id: I0cf4ccfced13b0d32b3d20713eace63e66945332 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-08soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualificationKrishna Prasad Bhat
USBSUSPGQDIS is a disqualifier bit which will allow platform to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this bit will ensure that USB2 PHY SUS is power gated before entering s0ix. BUG=b:175767084 BRANCH=dedede TEST=s0ix works on drawcia and USB wake from s0ix works fine. Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-07ACPI: Remove ACPI_NO_SMI_GNVSKyösti Mälkki
This was used as a guard to not raise SMI with APM_CNT_GNVS_UPDATE. The handler has been removed now completely. Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-07soc/amd/picasso: Add GRXS and GTXS methodEric Lai
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-07soc/amd/picasso: Add STXS and CTXS methodEric Lai
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/zork: Decrease stamp_boost parameter for dirinbozKevin Chiu
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec) To pass balance performance and skin temperature test, decrease stamp_boost: 2500 -> 1640 BUG=b:175364713 TEST=1. emerge-zork coreboot 2. run balance performance and skin temperature test Change-Id: I44f086af6b5dd552efd2bd1ef4db0d69b652826d Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-01-07security/intel/txt: Don't run SCHECK on CBnTArthur Heymans
This functionality only exists on legacy TXT. Change-Id: I4206ba65fafbe3d4dda626a8807e415ce6d64633 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07mb/google/dedede: Add support for charger throttlingSumeet Pawnikar
Add charger current throttling support for dedede baseboard BUG=None BRANCH=None TEST=Built and tested on boten system Change-Id: I79edba579249111294a982590660196f05be7eaf Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49083 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07arch/x86: Move prologue to .init sectionKyösti Mälkki
For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07cpu/intel/haswell: Rename `HASWELL_BCLK` to `CPU_BCLK`Angel Pons
This is just to ease merging with Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I9239489fe48f04714e6626b57ef07ca8b3013024 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46910 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/asrock/h110m: Remove MAINBOARD_POWER_ON_AFTER_POWER_FAILMartin Roth
The MAINBOARD_POWER_ON_AFTER_POWER_FAIL symbol was removed in Commit 9faae2b939. The default is currently to keep power off after a power failure. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47671 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07soc/intel/icelake: Remove unused ENABLE_DISPLAY_OVER_EXT_PCIE_GFXSubrata Banik
Mainboard user can select VGA_ROM_RUN_DEFAULT Kconfig hence no need to have another ENABLE_DISPLAY_OVER_EXT_PCIE_GFX Kconfig to load/execute VGA OpRom. Change-Id: Id87f82d9c3657afad9db94b1ec0917121edfe2bb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49023 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/volteer/var/elemi: Tune i2c frequencyWisley Chen
Tuning i2c frequency for elemi I2C0: 396.6 KHz I2C1: 395.9 KHz I2C5: 397.1 KHz BUG=b:176794161 BRANCH=volteer TEST=emerge-voleteer coreboot, and measure i2c clock. Change-Id: I23b04a9b5ff8873d9de12e762e8e2786ef474ac0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-07mb/google/dedede/var/metaknight: update Goodix touch screen sequenceTim Chen
Update Goodix touch screen reset delay time to 180ms. BUG=b:176213670 TEST=Build and boot Metaknight to OS. Change-Id: I5801a36fb7c03b23046df16b1eaf4c548241bba5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/zork: Modify variant to Shuboz supportKane Chen
1. Add ELAN touchscreen/touchpad to overridetree.cb 2. Follow Dalboz setting to add variant.c BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ic3193ca7957251841e75a7e5c7a16fc5047919fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48001 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/intel/jasperlake_rvp: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make EC_GOOGLE_CHROMEEC_SWITCHES depend on VBOOT, rather than force selecting it. Change-Id: If96b2a935d2f7388a24be7d8e65c7dfc2c89a0fc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07mb/intel/adlrvp: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC depend on VBOOT, rather than force-select it. Change-Id: I0ec418d4182865636b6350f1ee151420d8e02c33 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-07mb/google/lindar: Fix building with CONFIG_CHROMEOS unsetMatt DeVillier
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it. Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKUMatt DeVillier
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal" SKU; this has nothing to do with building for ChromeOS or not, and by having this dependency, boards with select the CSE lite SKU are unable to build with CONFIG_CHROMEOS unset due to Kconfig dependency issues. Test: build google/wyvern with CONFIG_CHROMEOS not set. Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07mb/google/puff/var/dooly: Config I2C0 SerialIoDevModeTony Huang
I2C0 has amplifier connection, thus set it to PchSerialIoPci. BUG=b:170273526 BRANCH=puff TEST=Build and check PCH serial IO config is set I2C0 to Mode 1 Change-Id: I9540f7b5538d37de53bcf43531488d714874a565 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-01-07cpu/intel: add PC10 residency counter MSRMichael Niewöhner
This MSR will be used in the follow-up changes. Change-Id: Ia6f74861502d4a9f872b2bbbab2e5f1925a14c4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49044 Reviewed-by: Lance Zhao Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/razer/blade_stealth_kbl: Remove comments with pad functionsMaxim Polyakov
Remove these comments, because it does not contain useful information that helps to understand the circuit, which we do not have. Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical. Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-07mb/google/dedede/var/magolor: modify raydium touch screenRen Kuo
modify raydium touch screen power on timing to meet requirement BUG=b:174280232 TEST=build firmware and measured the timing Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I3ecc9d8e21f8c76e9e96cf050dcde83c3c4f4ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48971 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07mb/google/dedede/var/metaknight: Configure I2C high and low timesTim Chen
Configure the I2C bus high and low times for port0,2 and 4 I2C buses. BUG=b:176519792 TEST=Measured the I2C bus frequency lower than 400 KHz. Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/madoo: Update Goodix touchscreen power sequenceDtrain Hsu
Follow Goodix datasheet (GT7375 Programming Guide_Rev.0.1.pdf and GT7375P Programming Guide_Rev.0.6.pdf) to tune touchscreen power sequence. Increase reset_delay_ms from 120ms to 180ms. BUG=b:176511605 BRANCH=dedede TEST=Build and boot Madoo to OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iae35e4da31a3c3afd24c7daf81a5a3e762acd3b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-07mb/google/dedede/var/boten: Configure I2C high and low timeStanley Wu
Configure the I2C bus high and low time for all enabled I2C buses. BUG=b:168783630 TEST=Measured the I2C bus frequency reduce to 387 KHz. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/lantis: Config I2C high and low time for touchscreen/audioTony Huang
Config I2C high / low time in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). These tuning value is applied from touchpad as a base line, and EE measured touchscreen/audio runs at 399/396.7kHz after tuning. BUG=b:173709409 BRANCH=dedede TEST=Build and check after tuning I2C clock is under 400kHz Change-Id: I970d69e6361d7cf6fcfc4e5b0b3c5fbfa885367c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/dedede/var/lantis: Config I2C high and low time for touchpadTony Huang
BUG=b:173709409 BRANCH=dedede TEST=EE measured result is 390.8kHZ Change-Id: I7a6475fd29d4c9f8efa78a42a112b5565511b939 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07mb/google/zork/var/vilboz: Fix Goodix touchscreen power sequenceFrank Wu
According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop delay time from 100 ms to 160 ms. The power sequence is not met with the latest guide_rev.0.6. BUG=b:176270381 BRANCH=zork TEST=Confirm the measured waveform complies with Goodix touchscreen spec. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07soc/mediatek: rtc: Use `bool` as return typeYidi Lin
BUG=b:176307061 TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot boot to shell on Asurada Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-06soc/intel/broadwell: Move MAX_CPUS from mb to SoCFelix Singer
All Broadwell boards use 8 for MAX_CPUS, so this option can be factored out into SoC Kconfig. Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/skylake: Move MAX_CPUS from mb to SoCFelix Singer
Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8Angel Pons
Haswell and Broadwell have at most 8 threads. Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46952 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06mb/google/volteer/var/voema: Update Aux settings for Port 0David Wu
On Voema port 0 (MB PORT) does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. BUG=b:176462544 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-01-06mb/amd/mandolin/mainboard: Remove unused pirq_dataRaul E Rangel
This table was wrong. It's also produced by the SoC code now. BUG=b:170595019 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac Reviewed-on: https://review.coreboot.org/c/coreboot/+/48667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06mb/google/zork/mainboard: Remove unused pirq_dataRaul E Rangel
This table was wrong. It's also produced by the SoC code now. BUG=b:170595019 TEST=Verify PCI IRQ: log messages Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06soc/amd/picasso: Correctly populate the PCI interrupt line registerRaul E Rangel
The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06soc/amd/picasso: Fix ACPI PCI routing tableRaul E Rangel
The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account. Now that we know how AGESA programs the routing table we can correctly generate it. We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts. There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard. BUG=b:170595019 TEST=Used ezkinil Boot kernel with `pci=nomsi amd_iommu=off noapic` and `pci=nomsi amd_iommu=off` then verified system was usable and verified /proc/interrupts looked correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06soc/amd/picasso/root_complex: add missing set_resourcesFelix Held
The set_resources field in the root_complex_operations struct shouldn't be NULL, but a pointer to noop_set_resources instead. This fixes the error "PCI: 00:00.0 missing set_resources". Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-06soc/amd/common/block/gpio_banks: fix sequence in gpio_outputFelix Held
When configuring a GPIO pin as output the value should be written before it gets configures as an output to avoid a possible glitch on the output when the GPIO pin was an input before and the output value was different from the one that got written afterwards. Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06soc/amd/common/block/gpio_banks: clear output enable in gpio_input_*Felix Held
The functions to configure a GPIO as input with pull-up/down need to clear the output enable bit, so that the direction will be input. If the pin was configured as output before, the pin direction was still output after this call which is at least unexpected. Change-Id: Id1fa1669195080b34fd62324616825415728b0b4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06soc/amd/common/block/gpio_banks: clear pull-up/down bits in gpio_inputFelix Held
If the pin was configured as pull-up/down before this wouldn't get cleared when calling gpio_input before. Change-Id: I17d5eccb7492138e64abaecbd7cb853adb8c4d2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06cpu/intel/model_206ax: Simplify C-state acpigenAngel Pons
Since there's only one set of values, the if-clause is unnecessary. Change-Id: I2fb4582377fe2f204d2cee0dc513a4d5d24feabe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-06cpu/intel/model_206ax: Rename `cX_acpower` optionsAngel Pons
They aren't specific to AC power operation anymore. Also adapt autoport. Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06cpu/intel/model_206ax: Unify ACPI C-state optionsAngel Pons
All mainboards use the same values for AC and battery, even desktop boards without a battery. Use the AC values everywhere and drop the battery values. Subsequent commits will rename the AC power options accordingly, and will also clean up the corresponding acpigen code. This is intentional so as to ease reviewing the devicetree changes. Also update util/autoport accordingly. Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-06cpu/intel/x/chip.h: Drop unused `disable_acpi` settingAngel Pons
It is not used anywhere. Drop it. Change-Id: I92a72a46db237cf855491a664cdfadca34306f6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49087 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06nb/intel/sandybridge: Use consistent comment styleAngel Pons
Change-Id: Iacb1fb0a1309c3c23e670fee540514b6f546314a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-06nb/intel/sandybridge: Define and use `QCLK_PI` constantAngel Pons
To allow adjusting the phase shift of the various I/O signals, the memory controller contains several PIs (Phase Interpolators). These devices subdivide a QCLK (quarter of a clock cycle) in 64 `ticks`, and the desired phase shift is specified in a register. For shifts larger than one QCLK, there are `logic delay` registers, which allow shifting a whole number of QCLKs in addition to the PI phase shift. The number of PI ticks in a QCLK is often used in raminit calculations. Define the `QCLK_PI` macro and use it in place of magic numbers. In addition, add macros for other commonly-used values that use `QCLK_PI` to avoid unnecessarily repeating `2 * QCLK_PI`, such as `CCC_MAX_PI`. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Id6ba32eb1278ef71cecb7e63bd8a95d17430ae54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-01-06soc/intel/alderlake: Update CPU microcode patch base address/sizeSubrata Banik
This patch updates CPU microcode patch base address/size to FSP-S UPD to have second microcode patch loaded successfully to enable Mcheck flow. This is new feature requirement for ADL as per new Mcheck initialization flow. BUG=b:176551651 TEST=Able to reach beyond PC6 without any MCE. Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-14 21:54:46 +0000