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2015-08-07via/nano: Move CPU microcode to 3rdparty/blobsStefan Reinauer
Change-Id: I5da2a9fc34d2108caa2f21c0883d209b03a6b872 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11132 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-07vendorcode: Move AMD sources from blobs to vendorcodeMarc Jones
The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode and fix Kconfig and Makefile.inc to match. Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-07amd/model_fxx: Move CPU microcode to 3rdparty/blobsStefan Reinauer
Change-Id: I1a772be9d72aa6d6552f5ba21c20b28e400677e9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11131 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-07amd/model_10xxx: Move CPU microcode to 3rdparty/blobsStefan Reinauer
Change-Id: Ib053bdec185eca2b45c95bec713cf0fb6d16c0bc Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11130 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-08-05vendorcode: Fixup AGESA PI Kconfig variablesMarc Jones
The *_SELECTED Kconfig variables are not needed with the options contained within "if CPU_AMD_AGESA_BINARY_PI" introduced in e4c17ce8. It also removes the need to source and select the default prior to selecting the AGESA source or AGESA PI option. Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-04x86: Make sure boot device is mapped below 4GStefan Reinauer
On x86-64 the current way of calculating the base address of the boot device (SPI flash) gets an unwanted sign extension, making it live somewhere at the end of 64bit address space. Enforce rom_base to be at the upper end of the 4G address space. Change-Id: Ia81e82094d3c51f6c10e02b4b0df2f3e1519d39e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-30gigabyte/ga-b75m-d3h: Update device treeDamien Zammit
This patch resolves the outstanding issues with PCI device enumeration and getting the board to boot into GNU/Linux with VGA rom. Previously the board would not boot to GNU/Linux with video, even if VGA rom was used. Bugs in the devicetree were fixed according to superiotool output. Tested on GA-B75M-D3H with VGA rom. Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64) Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10895 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-30vendorcode: 64bit fixes for AMD CIMX SB800Stefan Reinauer
Make SB800 code compile with x64 compiler These fixes probably apply 1:1 to the other SB components in that directory. Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10573 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30vendorcode: Port AMD Agesa for Fam14 to 64bitStefan Reinauer
Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10581 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30SB800: Port to 64bitStefan Reinauer
Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10582 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30amd/bettong: Enable fan controlWANG Siyuan
1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but does not work on Windows 8, so I didn't use it. After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. 3. Fan control works on Bettong. I used "APU Validation Toolkit" to test on Windows 8. This tool can put load to APU. The fan's behaviour is just like bettong/fchec.c defined. When the temperature is 40 Celsius, the fan start to run. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10721 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-30AMD binary PI: add southbridge support for fan controlWANG Siyuan
1. Add functions to support fan control. 2. When IMC firmware is added, the current firmwares' layout cause build error. There is not enough space to add some firmwares, so HUDSON_PSP_OFFSET is added to fix this problem. Change-Id: Ie470a88cb9da256d9f72ea56bf268c15df195784 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10720 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-30AMD binary PI: add vendorcode support for fan controlWANG Siyuan
Binary PI doesn't provide fan control lib. HwmLateService.c and ImcLib.c are ported from Kabini PI. I have tested on AMD Bettong. The two files work. Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10719 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-29skylake: Update microcode reload in ramstage.Rizwan Qureshi
For Skylake, Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootclock and ramstage (MP init). Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:287513 Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287674 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11056 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29Add SoC specific microcode update check in ramstageRizwan Qureshi
Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid reloading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11055 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29Skylake: Fix microcode reload in bootblock cpu initRizwan Qureshi
If Skylake microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If this is supported the FIT microcode load will set the msr (0x08b) with the patch ID one less than the ID in the microcode binary. This results in microcode getting reloaded again in the bootblock cpu init. Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286054 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11052 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-29arm, arm64, mips: Add rough static stack size checks with -Wstack-usageJulius Werner
We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: clean-up pei_datarobbie zhang
Remove the items that are obviously broadwell left or become no-need with fsp. BUG=chrome-os-partner:43186 BRANCH=None TEST=build and boot on sklrvp3. Signed-off-by: robbie zhang <robbie.zhang@intel.com> Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010 Original-Reviewed-on: https://chromium-review.googlesource.com/288833 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: align power management names with hardwareAaron Durbin
Some of the field and register names in the power management code were not reflecting current chipset documentation. While in there fix 0-sized array in the power_state structure. Lastly, log the entire STD GPE register for visibility in elog. It reports as an extension of other GPIO wake events. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288296 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: provide pcr helper to get a port's register spaceAaron Durbin
In order to aid users of the PCR register space provide pcr_port_regs(). BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0 Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288193 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: prefix the gpio functions with 'gpio_'Aaron Durbin
In order to provide more clarity on what some of the gpio functions are doing add a 'gpio_' prefix to the globally visible functions. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288192 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11067 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: remove unused types and definitions in gpio.hAaron Durbin
These types and definitions were carried over from a previous platform. However, they are not used. Remove them. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built on glados Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c Original-Signed-off-by: Aaron Durbin <adurbin@chormium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288191 Original-Trybot-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29t210: lp0_resume: implement MBIST workaroundYen Lin
As in cold boot path, implement MBIST workaround in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: I997009ecb0f52fb5a47c62b8daea33e472ec2664 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4b1f80ea4c1d3782eb9f2c90c2a8d7b2e97ba050 Original-Change-Id: Ib4944401e1df02bf0aab1e78db7e14ef56c7f829 Original-Reviewed-on: https://chromium-review.googlesource.com/287287 Original-Tested-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/11071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29veyron_rialto: Select PHYSICAL_REC_SWITCHJonathan Dixon
Copied from Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 BUG=chrome-os-partner:43022 BRANCH=None TEST=Used physical recovery button to enter dev mode on rialto Change-Id: I39fd13fee3b9f272f3dc08a447091e05a3d74741 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: eed0652f84cba963044908bb91aac7b8c1c81fd4 Original-Signed-off-by: Jonathan Dixon <joth@chromium.org> Original-Change-Id: I388d8bb0faa93b54540be095e68450192592a093 Original-Reviewed-on: https://chromium-review.googlesource.com/287660 Original-Reviewed-by: Jason Simmons <jsimmons@chromium.org> Reviewed-on: http://review.coreboot.org/11069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29veyron: update mickey sdram-lpddr3-samsung-2GB.incjinkun.hong
Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This resolves an issue that was observed on some Mickey boards with the Samsung 2GB LPDDR3 and is believed to be caused by inferior routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.) BUG=chrome-os-partner:41905 TEST=Boot from mickey BRANCH=None Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286333 Reviewed-on: http://review.coreboot.org/11051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29Revert "smaug: Do not gate XUSB partitions"Andrew Bresticker
The PLLU and UTMIPLL power-up sequences have been fixed in the kernel. It's no longer necessary for the XUSB partitions to be ungated at boot. This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7. BUG=chrome-os-partner:41244 TEST=Build and boot on Smaug; xHCI still works. BRANCH=none CQ-DEPEND=CL:282765 Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286810 Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Mark Kuo <mkuo@nvidia.com> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/11050 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29intel/braswell: fix buildJenny TC
Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained additions to braswell's chip.h which were lost during merging. BRANCH=None BUG=None TEST=google/strago builds Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912 Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e Original-Original-Signed-off-by: Jenny TC <jenny.tc@intel.com> Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155 Original-Reviewed-on: https://chromium-review.googlesource.com/288880 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29BCRD2: Enable PMIC SVID configJenny TC
Enable PMIC SVID config for BCRD2 based on board id. UPD parameter is used to select the SVID config and PMIC I2C bus number BRANCH=None BUG=None TEST=Build and boot the system Change-Id: I3c4c06bd25c241abdf46aa14af74eecf77cf77a6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 10bb8d4ad96d1187f6e135ca1535d70ae45ee887 Original-Change-Id: I9191db7bace4f4840e3c32381093c6c0806f7c32 Original-Signed-off-by: Jenny TC <jenny.tc@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282156 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29google/stout: Implement functions required by CHROMEOSPatrick Georgi
BRANCH=none BUG=chromium:513990 TEST=google/stout builds Change-Id: I00de7524297e4471a9f7d6afd0d2b991d29020e9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: b85c54af7d4def45f014ee1d9b79df0b649f90f7 Original-Change-Id: I0870dd11c97cecc932a135f73be8234a88c0622b Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288860 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29google/parrot: Implement functions required by CHROMEOSPatrick Georgi
BRANCH=none BUG=chromium:513990 TEST=google/parrot builds Change-Id: I5e354d6160e554f1c41e84eac6102e84de34b81d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: d5a6253e6f19815736a6b433f6c58e3be2e5841b Original-Change-Id: I3a3bf9ead333d56472f856c9efefff239fb70586 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288852 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29google/butterfly: Implement functions required by CHROMEOSPatrick Georgi
BRANCH=none BUG=chromium:513990 TEST=google/butterfly builds Change-Id: Ia678ca4b0778ee4a2e55ba44a5d89ac6dd691b35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 0d82ea2090fae9c66f41ee05cc20a9b22d3641c0 Original-Change-Id: I2fea10c17b769ca76b9d0b80978b4c512ed8c680 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288851 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29intel/haswell: fix CHROMEOS builds for haswellPatrick Georgi
Compiler complained about potentially uninitialized variable. Fixes google/bolt, google/falco, google/panther, google/slippy BRANCH=none BUG=chromium:513990 TEST=the mentioned boards build with CONFIG_CHROMEOS=y Change-Id: Ia28c833bd6ef8e1f7c820a61b41ce456eba51246 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4566c355cc6828ab96e8d52bfad6ccbf6be6f7ce Original-Change-Id: I4d9a685373362f8a092b325efee3f816c056c708 Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288850 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-29skylake: remove the redundant fspNotify in chip final.robbie zhang
The fspNotify(EnumInitPhaseAfterPciEnumeration) is already registered in fsp_util.c as a generic callback, this is some code left from early development. Also I don't see a need for the chip_final function, although we could keep it as a placeholder but i decided to remove it. BUG=chrome-os-partner:42979 BRANCH=None TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3. Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7 Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287991 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11054 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-29skylake: Rework microcode include pathDuncan Laurie
Remove the microcode include path config options and include the mainboard blob directory by default. BUG=chrome-os-partner:42109 BRANCH=none TEST=emerge-glados coreboot CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922 Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448 Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285150 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11053 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-27arch/x86: make dependency explicitPatrick Georgi
bootblock.inc requires config.h to be around which may need to be created. Have make be aware of it. Change-Id: I79ad003b461d7da7a5afecdae55fdd07ba735821 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-24glados: Support reading memory strap GPIOs to select SPDDuncan Laurie
Add some board specific code to enable the memory configuration GPIOs in GPIO input mode and read them to determine which memory type is on the board. Also add the other memory types that are not yet present in the glados mainboard directory. This should be replaced with the real gpio infrastructure once it is ready. BUG=chrome-os-partner:43069 BRANCH=none TEST=build and boot on glados Change-Id: I7a9ce10e92ad6681528572e87b6cfee29880841a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d81e969c5950fd89bb745d1403abddb08a942f83 Original-Change-Id: Iffb0bd5c176f2adbdd9302d9bff5b7bde725d671 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287436 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24skylake: Fix building without serial consoleDuncan Laurie
In order to build without CONFIG_CONSOLE_SERIAL the Skylake SOC Kconfig should not be enabling serial console by default. Also fix other compile issues when serial console is disabled. BUG=chrome-os-partner:40857 BRANCH=none TEST=build glados without serial console enabled Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55 Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287438 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11043 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24glados: Enable internal pullup for EC_IN_RWDuncan Laurie
Enable 20K internal pullup for the EC_IN_RW GPIO. BUG=chrome-os-partner:42285 BRANCH=none TEST=build and boot on glados Change-Id: I499164fb5050d350510072d2a06eb97fb7f9fcb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e2de7d4800797a1585165a34dd39af3d635b1f55 Original-Change-Id: I7af1b78482197701aa452998106c2c3476fcc330 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287437 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11045 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24glados: Add ACPI configs for speaker amps and codecBen Zhang
The audio codec nau8825 and two ssm4567 speaker amps are instantiated via ACPI. BUG=chrome-os-partner:41280 BRANCH=none TEST=The devices are instantiated. Speaker/headphone playback works on glados. Change-Id: I1297c2435b3051dd749ad7de324b64ba1504cf09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59e5eb2682a2fc2cb58068dfcb6dd2415d43b286 Original-Change-Id: Ib7ec8c868251601f67cdf365cd3e935d256c8ac5 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-24rockchip: rk3288: extend jerry backlight vcc_led delay timehuang lin
some jerry panels need more delay time between the vcc_led and bl_en, so we extend the delay time from 20ms to 120ms. BUG=chrome-os-partner:42997 TEST=Boot from jerry, and do not flicker again BRANCH=none Change-Id: Ifcf84578038eb5c2e5a0dfae936ee63cef671968 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b00b6bd108f0aae461085d00819eca08ec892b3 Original-Change-Id: I74999601b41ccac22493cc9cd0bf52cd4dbb8c26 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287373 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-24tegra210: Fix parameter order of write32()Stefan Reinauer
The correct function prototype is void write32(void *addr, uint32_t val) BUG=chrome-os-partner:38073 BRANCH=none TEST=build lp0 code and see it succeed. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: Icadc9e2d142e5a222509e894f43b0c8a70eed031 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46635d9d3ee1ca364e7ad6d6dd7ea9efa9dedbc Original-Change-Id: Id2b6847af80dfddcb3b7133a663becb78ed477ba Original-Reviewed-on: https://chromium-review.googlesource.com/285544 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11049 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-24tegra lp0: fix checkpatch errorsStefan Reinauer
The checkpatch.pl scripts complains about the placing of the inline keyword: ERROR: inline keyword should sit between storage class and type Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:38073 BRANCH=none TEST=repo upload works ;) Change-Id: Ibd2b8a437eda2fc720f8fc32c5821bae3be41d12 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20c0d34240966d5ae39c1667d4486b4341e183b Original-Change-Id: I36d600c4677c622c334d849bf260323592a8a4fc Original-Reviewed-on: https://chromium-review.googlesource.com/285543 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/11048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23sklrvp: Add board_info fileStefan Reinauer
Change-Id: I658f88189857e25dde474d59875650f72c680818 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10972 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-23nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10hJonathan A. Kollasch
Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10984 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-07-23t210: audio: add CLK_V_EXTPERIPH1 clockYen Lin
For audio to work, need to enable CLK_V_EXTPERIPH1 clock. This CL is needed because after MBIST workaround is applied, CLK_V_EXTPERIPH1 clock is default to be off. BUG=None BRANCH=None TEST=Tested on Smaug, hear beep when press Ctrl+U at serial console when DEV screen is showing Change-Id: I32dccc0c7983f8fa86812d845a2f00ac9881d521 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 149d04e6ba642734d5ea36cac8206fad3ac13ce0 Original-Change-Id: Ifa1afb0798c1039c8ea9084b5a7ee3b09b4d70ac Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285604 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11041 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: Enable WRAP to INCR burst type conversion in MSELECTYen Lin
Enable WRAP to INCR burst type conversion in MSELECT. MSELECT CONFIG register can only be accessed by CPU. So do it in ramstage when CPU is started. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: Iee05531c45e566f47af24870be6068247c2d9a00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 21d9e4d3a8827f7bba57c03ca36b702aaba1ce20 Original-Change-Id: I6a241455b28f24b8756ad09bf7605a2e7e52af57 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282418 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11040 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: implement MBIST workaroundYen Lin
MBIST has left some registers in non-suggested states. This CL restores CAR CE's, SLCG overrides & PLLD settings. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I1ddb19dd9fb6d8fb4d36e67eedeb847c6fd9f774 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37a1c90c6deb351b2ae2caa03e5076553126744b Original-Change-Id: I613b4ef622d64305d436cb8379a5170b0fe1c9af Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282417 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
Like in cold boot path, need to set CAR2PMC_CPU_ACK_WIDTH to 0 in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: Iffd7fa4d0266e2ec482ec17e5203ceff8afe748f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 052b649b1e6a4e34d621d710ee43aec7149ab8a8 Original-Change-Id: Icdf9879469485fb37b820b30c9663eda528ac013 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286600 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/11037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23t210: change memlayout.ldYen Lin
MBIST workaround needs more space in bootblock. bootblock += 4KB; romstage -= 4KB BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I8338d0a134185a425af36e302dcf0ed1520b7e21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 388523bf4fa25ff3ecf9607ff36ce7c6109485ed Original-Change-Id: Ib08f2ff438f9d96a19b44af1b3e13260966f98f1 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287286 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11038 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-23google/veyron_rialto: enable VIRTUAL_DEV_SWITCHJonathan Dixon
BUG=chrome-os-partner:43022 TEST=None BRANCH=None Change-Id: I41c904603e7213da1c8d8e0945b572f6ba844031 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d91722317ffc55a4848e8e3bdac8412218fe1dc4 Original-Change-Id: I1ed4c7aaa35158815f8f7a94eafb77db55a381d0 Original-Signed-off-by: Jonathan Dixon <joth@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287300 Original-Reviewed-by: Jason Simmons <jsimmons@chromium.org> Original-Reviewed-by: Karl Townsend <karlt@chromium.org> Reviewed-on: http://review.coreboot.org/11036 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 16:52:20 +0000