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2015-07-14fmap: Introduce new function to derive fmap name from offset/sizePatrick Georgi
vboot passes around the offset and size of the region to use in later stages. To assign more meaning to this pair, provide a function that returns the fmap area name if there's a precise match (and an error otherwise). Change-Id: I5724b860271025c8cb8b390ecbd33352ea779660 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10865 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14getac/p470: initialize timestamps in romstagePatrick Georgi
Change-Id: I2f43684bbdd48f30039fe09275043ddf203d447c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10907 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-14azalia: fix up and clean up shrinkage of boilerplate codeJonathan A. Kollasch
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14amd/rs780: Fix typoPatrick Georgi
Change-Id: I08f7251f8fc42b9028b1fdb830546f9922ef43aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: YongGon Kim <ilios86@gmail.com> Reviewed-on: http://review.coreboot.org/10914 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-14intel/sandybridge/gma: Add graphics PCI Device IDs 0x0162 and 0x0152Damien Zammit
Change-Id: Ide0fd757cdd31a5b5ff184f7ab2d48e62ea50015 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10896 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-14amd/fam10: Add k10temp ACPI thermal zone mixin.Tobias Diedrich
This ACPI thermal zone is applicable to AMD family 10 to 14 (and some 15) CPUs. It should not be used on boards for which errata 319 (The thermal sensor of Socket F/AM2+ processors may be unreliable) is applicable. AM3 and later should be fine. Derived from src/northbridge/amd/amdk8/thermal_mixin.asl Change-Id: Id036cbf4cd717c3320a720edc452945df2b5e072 Signed-off-by: <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10617 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-07-13x86: flatten hierarchyStefan Reinauer
It never made sense to have bootblock_* in init, but pirq_routing.c in boot, and some ld scripts on the main level while others live in subdirectories. This patch flattens the directory hierarchy and makes x86 more similar to the other architectures. Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10901 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-13x86: Port x86 over to compile cleanly with x86-64Stefan Reinauer
Change-Id: I26f1bbf027435be593f11bce4780111dcaf7cb86 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10586 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-13superio/smsc: Add support for SMSC DME1737Jonathan A. Kollasch
Change-Id: If2ba9ca48c809fe4f7dc0595a3cb3df168d630fd Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10893 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13superio/smsc/dme1737: copy superio/smsc/lpc47b397Jonathan A. Kollasch
Change-Id: I3218bfaaa64bcad54fe97c6f887025356ccc9356 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10892 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13tegra124/tegra210: Include stages.h in bootblock.cStefan Reinauer
Needed for the main() prototype Change-Id: I921a77d8b131b751291d3a279b23ee18b13eca8d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10862 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13tegra210: Fix coding style in clock.cStefan Reinauer
Change-Id: I1a8ce0b8ec291a5ddd8fdefcda24842e2a3c692d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13smaug: Set LDO2 voltage to 1.8VFurquan Shaikh
LDO2 regulator is used as an always-on reference for the droop alert circuit. Set output voltage to match kernel settings. CQ-DEPEND=CL:284649 BUG=chrome-os-partner:42305 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284879 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10900 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-13t210: Apply A57 hardware issue workaround during cpu startupFurquan Shaikh
Define custom stage_entry to apply workaround for A57 hardware issue for power on reset. It is observed that BTB contains stale data after power on reset. This could lead to unexpected branching and crashes at random intervals during the boot flow. Thus, invalidate the BTB immediately after power on reset. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware for 10K iterations. Change-Id: Ifbc9667bc5556112374f35733192b67b64a345d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc7c2fec3c6b29e291235669ba9f22ff611064a7 Original-Change-Id: I1f5714074afdfee64b88cea8a394936ca848634b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13arm64: Define stage_entry as weak symbolFurquan Shaikh
This allows SoCs/CPUs to have custom stage_entry in order to apply any fixups that need to run before standard cpu reset procedure. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully Change-Id: Iaae7636349140664b19e81b0082017b63b13f45b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 498d04b0e9a3394943f03cad603c30ae8b3805d4 Original-Change-Id: I9a005502d4cfcb76017dcae3a655efc0c8814a93 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284867 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10897 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13arm64/a57: Move cortex_a57.h under include directoryFurquan Shaikh
BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully Change-Id: I8a94176a3faacb25ae5e9eaeaac4011ddf5af6a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 802cba6f28a4e683256e8ce9fb6395acecdc9397 Original-Change-Id: I3a5983d4a40466bc0aa8ab3bd8430ab6cdd093cc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284868 Original-Reviewed-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10898 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13t210: Add TZDRAM_BASE param to BL31_MAKEARGSFurquan Shaikh
1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13intel raminit: improve loggingPatrick Rudolph
Print the old timB value to observes changes made. Change-Id: Iecec4918f1d95560b6e7933a169ccce83fcf073d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10891 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13intel raminit: fix timB high adjust calculationPatrick Rudolph
Issue observed: Any memory DIMM placed in channel0 slots stops at "c320c discovery failed". The same memory DIMM works when placed in channel1 slots. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMMs: * elixir 1GB 1Rx8 PC3-10600U M2Y1G64CB88A5N * crucial 2GB 256Mx64 CT2566aBA160BJ * corsair 8GB CMZ16GX3M2A1866C9 Problem description: In case of good timmings (all bits are set) an offset of 3*64 was applied. The following test (c320c discovery) failed only on those byte-lanes. Problem solution: Don't modify timB in case of good timings measured. Final testing result: The system boots with every DIMM placed in channel 0 slots. Change-Id: Iea426ea4470640ce254f16e958a395644ff1a55c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10889 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13intel raminit: whitespace fixesPatrick Rudolph
Remove whitespace errors. Change-Id: If69244a5d47424e3e984fdf782ea9d2d3c466d86 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10888 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-13intel sandybridge: add VGA pci device idPatrick Rudolph
Add VGA pci device id 0x0152 for Intel IvyBridge CPUs. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: Ia546fdf0cc3bbd4c0ef6b5fd969232f105bceb22 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: http://review.coreboot.org/10798 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-07-12Verify Kconfigs symbols are not zero for hex and int type symbolsMartin Roth
For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead check to make sure they're defined and not zero. In some cases, zero might be a valid value, but it didn't look like zero was valid in these cases. Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-12southbridge/amd/pi/hudson: Fix HUDSON_DISABLE_IMC kconfig warningMartin Roth
Platforms selecting the HUDSON_DISABLE_IMC symbol were showing the warning: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_AMD_AGESA_BINARY_PI) selects HUDSON_DISABLE_IMC which has unmet direct dependencies (SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN) By moving the definition of the symbol outside of the if block and removing the default n, we can get rid of the warning without changing the value for any platform. Change-Id: I5c1bdfbcf3c5c44ee05b8c5e679f6854d784d8dc Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10680 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2015-07-12x86emu/debug.h: remove #ifdef CONFIG_DEFAULT_CONSOLE_LOGLEVELMartin Roth
This protection didn't make sense to me - it seems like things would probably break if printf wasn't defined anyway. Change-Id: Ifb6bad46e193b35c13b7ad4946511fec74beff92 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-12Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()Martin Roth
Kconfigs symbols of type bool are always defined, and can be tested with the IS_ENABLED() macro. symbol type except string. Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-11amd/.../hudson: Warn if HUDSON_FWM_POSITION is not inside CBFSMartin Roth
Display a warning if CONFIG_HUDSON_FWM_POSITION is not inside CBFS. This can be extended to other Kconfig values for CBFS. Change-Id: I2423f7b361dda8aac5dab409fa7b656de486f635 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10683 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11Calculate HUDSON_FWM_POSITION and display warning on mismatchMartin Roth
This patch calculates the address where the chipset firmware descriptor should be located and compares it against the actual value from Kconfig. If the two don't match, it puts up a warning. This could probably replace the config variable completely, but I wanted to see how other people felt before doing that. I seem to recall that the value used to be calculated, so I figure that there must be a reason it's done this way at this point. If we do want to keep the Kconfig setting, this patch could also be modified to just verify that the HUDSON_FWM_POSITION is inside the ROM space. Change-Id: I94addf463e2c694a94eef218ec855103a3bb5da5 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10682 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-11arch/x86/Makefile.inc: Calculate CBFS_BASE_ADDRESS variableMartin Roth
The CBFS_BASE_ADDRESS can be compared against values used with cbfstool to generate warnings. This can help cut down on mistakes and debug time. Change-Id: I149007dd637661f799a0f2cdb079d11df726ca86 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10681 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-10timestamps: don't drop ramstage timestamps with EARLY_CBMEM_INITAaron Durbin
While running ramstage with the EARLY_CBMEM_INIT config the timestamp cache was re-initialized and subsequently used. The result was that the ramstage timestamps would be dropped from cbmem. The reason is that the ramstage timestamps perpetually lived in ramstage BSS never getting sync'd back into cbmem. The fix is to honor the cache state in ramstage in the timestamp_init() path. Also, make cache_state a fixed bit width to allow for different architectures across the pre-ramstage stages. TEST=Used qemu-armv7 as a test harness with debugging info. Change-Id: Ibb276e513278e81cb741b1e1f6dbd1e8051cc907 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10880 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-10include/cbmem_id.h: Add name for `CBMEM_ID_TCPA_LOG`Paul Menzel
Fix up commit f44ac13d (Add TCPA table.) by adding an entry for `CBMEM_ID_TCPA_LOG` to the macro `CBMEM_ID_TO_NAME_TABLE`. Currently, printing the CBMEM table of contents the name is missing. $ sudo cbmem -l CBMEM table of contents: ID START LENGTH […] 6. 54435041 c7fa8ff8 00010000 […] Adding an entry and rebuilding the utility cbmem, the name `TCPA_LOG` is shown. $ sudo cbmem -l CBMEM table of contents: ID START LENGTH […] 6. TCPA LOG c7fa8ff8 00010000 […] Change-Id: I089ea714349e07b322330bc11f723cc031c61c56 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10856 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-10include/cbmem_id.h: Sort `CBMEM_ID_TCPA_LOG` entryPaul Menzel
Fix up commit f44ac13d (Add TCPA table.) by moving the entry to the correct position so that all entries are sorted. Change-Id: Ib68deb525a942051e1063ea2ec0a3e3b4a937024 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-10Braswell: Move the microcode into a subdirectoryLee Leahy
Include the microcode files from the microcode subdirectory. BRANCH=none BUG=None TEST=Build and run on cyan. Change-Id: I4c8bf64d221d9ead18f1b7d6e1f01f61d88c9b25 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-10FSP 1.1: Update the CBFS image typeLee Leahy
Update Makefile.inc to use the simplified CBFS image type. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Ibb8413ab90b147e9d26d32639a8822c57ca54a46 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-09arm: add __umoddi3() to libgcc implementationStefan Reinauer
Change-Id: Ida01506406d1d74211f0155a84c2b25dbaac5f1c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10860 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-09rk3288: Fix & vs && mix up in hdmi driverStefan Reinauer
Change-Id: I54650671adaef3bc129c662d6e972474c869afaa Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10859 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-09device: remove unused x86 include from common codeStefan Reinauer
The include breaks compilation on ARM with clang. Change-Id: I1ce0d58dbcbb8785c23739670c8c9574c329a81c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10858 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-09arm: enhance eabi compat functionsStefan Reinauer
This fixes issues with our clang reference toolchain on ARM. Change-Id: Ib754941059285f15332bc694814aff6285969545 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10857 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-09ipq8064: enable timestamp collectionVadim Bendebury
One kilobyte of SRAM needs to be allocated and the feature enabled. BRANCH=storm BUG=chrome-os-partner:34161 TEST=timer error messages do not show up in the coreboot log any more Change-Id: I1d5e5521bf9ae495d4f4f50ff017c846a8420719 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ffb9bfb0cdfab1391f8ae07669a2ab6b24d88dd7 Original-Change-Id: I60066672334db36f5e7adbef6794d7afd177d292 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09veyron_{brain,danger,mickey,romy}: Select PHYSICAL_REC_SWITCHDavid Hendricks
BUG=chrome-os-partner:42220 BRANCH=veyron TEST=Used physical recovery button to enter dev mode on mickey Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283546 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09smaug: Update PMIC settingsFurquan Shaikh
Update PMIC settings as per table provided by hardware eng team. Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283543 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09arm64: Print sp value when dumping registers for exceptionFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully, sp verified during exception Change-Id: Idbeb93b1dbf163e2d86cd42369941ff98a3d2d9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca73b40f0248497143b6ab42bd0f5cc6cddf7713 Original-Change-Id: I38ee403200acb0e3d9015231c274568930b58987 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283542 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to workYen Lin
I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09veyron_danger: Enable developer mode switchDavid Hendricks
Danger has a physical developer mode switch, it was just never set up. This patch defines it, sets it up in fill_lb_gpios(), and disables VIRTUAL_DEV_SWITCH. Note: For now at least, dev mode is a bit wonky on Danger. It's connected to both a DIP switch and a button. The button is normally open, pulling dev mode high (defaulting to ON). The switch's "ON" position will pull the value low, so we invert the value in coreboot to see the expected behavior. Dev mode is enabled by holding the button down during boot or by setting switch 2 in the DIP bank to the ON position. BUG=none BRANCH=none TEST=toggled dev switch on Danger and saw dev screen show up (or not) as expected Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318 Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280852 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08vboot: Don't count boot attempts if lid is closedPatrick Georgi
This can be a problem with freshly updated devices that are periodically powered on while closed (as explained in the bug report). In this case, just don't count down. In case of actual errors (where we want the system to fall back to the old code), this now means that the retries have to happen with the lid open. Bump vboot's submodule revision for the vboot-side support of this. BUG=chromium:446945 TEST=to test the OS update side, follow the test protocol in https://code.google.com/p/chromium/issues/detail?id=446945#c43 With a servo, it can be sped up using the EC console interface to start the closed system - no need to wait 60min and plugging in power to get to that state. Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08vendorcode/intel/edk2: Fix EFI_PEI_GRAPHICS_INFO_HOB structureLee Leahy
Change the FrameBufferSize field from UINT64 to UINT32 to match the Platform Initialization 2.4 specification. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I28dc0608675ed5840863ecd15bd2f57e6b2f4c1d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10834 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08Braswell: Fix error in the warranty statementLee Leahy
Fix a cut and paste error in the warranty statement. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: If64b02f2c0fc2970932f23b99ad64beab5ab754e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10835 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-08memlayout: Add timestamp regions for t210 and cygnusStefan Reinauer
This is needed to make those SOCs compile with timestamps enabled. Change-Id: Iac20cb9911e1c76a18c8530385c9d7b8b46399e5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10833 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-07stddef.h: Disable check_member() macro when compiling with CLANGStefan Reinauer
CLANG assumes that _Static_assert() is a C++11 only feature and errs out when encountering the check_member macro complaining about a reinterpret_cast. Change-Id: Id8c6b47b4f5716e6184aec9e0bc4b0e1c7aaf17c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-07payloads: Reorganize Makefile.incs for external payloadsStefan Reinauer
This is not going as far as I would like it to go, but some of the external payloads have to be fixed up first. Long term, I would like to directly add payloads/external/* to subdirs-y and remove one layer of indirection from the build process. For now, moving the payload Makefile targets into payloads/ is already a small improvement. Change-Id: Ie4eb492eb804e0aaaf1a4d90af2f876f27a32a75 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10829 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 05:18:52 +0000