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2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-20google/mistral: Implement board resetsanthosh hassan
Implement reset using PSHOLD. Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c Signed-off-by: Santhosh Hassan <sahassan@google.com> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20mistral: qcs405: copy calibration data to CBMEMNitheesh Sekar
This patch adds support to copy the wifi calibration data to CBMEM so that the depthcharge can use it to populate the data into wifi dt node. Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-20soc/intel/cannonlake: Fix return values for get_param_valueFurquan Shaikh
Commit 41483c9 (soc/intel/cannonlake: Add required FSP UPD changes for CML) changed the enum values for PCH_SERIAL_IO_MODE so that 0 is invalid and valid values start from 1. However, get_param_value was not updated to correctly subtract 1 before returning any value. This change adds a macro PCH_SERIAL_IO_INDEX to apply the subtract 1 operation on any value that get_param_value needs to return. BUG=b:128946016 TEST=Verified that hatch boots successfully. Change-Id: I4e32fcd1efe4a535251f0ec58662a2dc5f70e8b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-19mb/google/hatch: Log EC events during S0ix resumeV Sowmya
This change adds support for logging EC events during S0ix resume. BUG=b:124131938 BRANCH=none TEST=Verified that the wake events are logged during the S0ix resume: 4 | 2019-03-05 07:55:27 | System Reset 5 | 2019-03-05 07:55:27 | Chrome OS Developer Mode 6 | 2019-03-05 07:56:54 | S0ix Enter 7 | 2019-03-05 07:57:09 | S0ix Exit 8 | 2019-03-05 07:57:09 | Wake Source | Power Button | 0 9 | 2019-03-05 07:57:09 | EC Event | Power Button Change-Id: I624f94c29bc66dbf4d9e1fec573d259985260ed3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-19src/southbridge/intel/i82801gx/pcie.c: Correct NULL checkJacob Garber
Check if `pcie_dev` is NULL instead of `dev`. This was flagged as REVERSE_INULL during a Coverity scan, but is a simple typo. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Idc40574b9341d1b10cb2136cbc1a865efa3ab3ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/31866 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19vboot: make vboot workbuf available to payloadJoel Kitching
Create a new cbtable entry called VBOOT_WORKBUF for storing a pointer to the vboot workbuf within the vboot_working_data structure. BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19soc/intel/icelake: Enable support for FSP 2.1 specificationSubrata Banik
Remove FSP 2.0 support from ICL SoC and add FSP 2.1 support. Change-Id: Ife0c133ddbf2e0fa14f94ffec15d11830cfaf7b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30158 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19drivers/intel/fsp2_0: Add support for FSP minor version updateSubrata Banik
This patch adds support for FSP2.1 Kconfig which is backward compatible with FSP2.0 specification and added below coreboot impacted features as below: 1. Remove FSP stack switch and use the same stack with boot firmware 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30310 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIsSubrata Banik
This patch ensures to have below listed features: 1. All required APIs to create MP service structure. 2. Function to get MP service PPI status MP specification here: http://github.com/tianocore/edk2/blob/master/MdePkg/Include/Ppi/MpServices.h coreboot design document here: ../Documentation/soc/intel/icelake/MultiProcessorInit.md Supported platform will call fill mp_services structure so that FSP can install the required PPI based on coreboot published structure. BRANCH=none BUG=b:74436746 TEST=Able to publish MP service PPI in coreboot. Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25634 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19rockchip/rk3399: Remove obsolete BL31 resource reservationJulius Werner
RK3399 SoC code still manually excludes the BL31 region from the memory map, even though that is now automatically done with the BL31() memlayout region. CB:31123 and CB:31538 just forgot to remove this line. The resulting memory map stays the same. Change-Id: I87458fa09f437b038af10e0fd9d76ef6d9394bc5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ting Shen <phoenixshen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-19mb/intel/coffeelake_rvp: remove double selection in KconfigThomas Heijligen
Change-Id: I0e1a66b3d1d7bd4633ad1df597f62ddbd38f46d4 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-19soc/intel/braswell: Use IRQ 9 for SCIFrans Hendriks
Default reserved value of used for SCI IRQ. Configure SCIS field to use IRQ 9. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-03-19mainboard: Add ASRock H110M-DVSMaxim Polyakov
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard. Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit. Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio. TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation. Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload. Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-19soc/intel/braswell/romstage: Drop unused 'include <rtc.h>'Elyes HAOUAS
Change-Id: I6577d9a31da44be5b57bb10497d9bd02fc9bbcd3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19src: Drop unused 'include <cbfs.h>'Elyes HAOUAS
Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19Fix 'unsigned int' to bare use of 'unsigned'Subrata Banik
Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-18mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKEShelley Chen
Move these configs to Kconfig.name as well. BUG=b:127310803 BRANCH=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-18qcs405: Add DRAM resourcesNitheesh Sekar
TEST=build Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18qcs405: Add Timer supportNitheesh Sekar
Init frequency to 19.2 MHz TEST=build Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18soc/qualcomm/qcs405: Add MMU supportNitheesh Sekar
Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18mainboard/google/mistral: Add support for MistralNitheesh Sekar
Adding a new board variant 'Mistral' based on qcs405 soc. TEST=build Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18soc/qualcomm/qcs405: Support for new SoCNitheesh Sekar
Adding the basic infrastruture soc support for qcs405 and a new build variant. TEST=build Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18soc/intel/braswell: Reserve IOAPIC and ROM resourcesFrans Hendriks
The mmio resouces IOAPIC and ROM area not reserved. Reserve IOAPIC and ROM resources. BUG=N/A TEST=Intel CherryHill CRB booting Embedded Linux Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-18mb/foxconn/g41m: Fix overridetreeKyösti Mälkki
The .chip_info field of PNP devices in overridetree incorrectly pointed to southbridge config structure in generated static.c files. Change-Id: If507c8ea9c865ff86e127226b93a8579bcf39d8d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-18src: Drop unused 'include <romstage_handoff.h>'Elyes HAOUAS
Change-Id: I311269967949533264e44fd3bb29ad3a06056653 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-18soc/intel/cannonlake: Pass coreboot debug interface info to FSPMaulik V Vaghela
coreboot have an option to use legacy UART or LPSS UART. FSP will use the UART initialized by coreboot and we can choose an option to skip Uart initialization by FSP. For this, we need to pass correct debug interface flag to FSP through which FSP will know which UART port to use. If we don't pass correct interface information, FSP may try to dump logs on that port and it may slow down the system. BUG=none BRANCH=none TEST=Compile and boot with coreboot. Check FSP and coreboot logs are coming on serial port. Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18include/cpu/x86/pae.h: Add missing includePatrick Rudolph
Add the include for size_t. Fixes compilation error on source files that do not include it. Change-Id: Ic752886d94db18de89b8b8a5e70cf03965aeb5c3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-18vboot: move assert in vboot_migrate_cbmemJoel Kitching
Fix a potential null pointer dereference when calling memcpy. assert should be before the memcpy call, and not after. BUG=b:124141368, b:124192753 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I5a2a99e906b9aa3bb33e1564d8d33a0aca7d06ac Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31923 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18src/nsc/common/nsc.h: Drop unused includeElyes HAOUAS
Change-Id: Id3501e65a9d0c0b5ad98679f5e78f985e87cbe55 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-18mb/(ICH7): Remove initialization already done at early_init.cElyes HAOUAS
V1CAP is a write-once register, and it is already programmed in intel/i945/early_init.c. Tested on 945G-M4 board (i945G + 82801GB). Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO)Elyes HAOUAS
SLOTCAP is R/WO, it becomes RO after the first write. Write already done on line #583. Tested using kprint before and after on 945G-M4 board. Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18ec/google/wilco: Enable software sync for VBOOTDuncan Laurie
Enable software sync by default if VBOOT is enabled. The slow update option is also needed, but this is moving to depthcharge so it is not defined here. Change-Id: I046661fae7315f84e96293532b4e1568558df962 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18ec/google/wilco: Fix handling of commands that do not respondDuncan Laurie
If the command does not respond the driver should not wait for it to complete before returning. Tested with SMI debug enabled to ensure that the final command does not report a failure. Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18soc/intel/common: Update ESPI disable optionDuncan Laurie
Update the Kconfig option for disabling ESPI SMI source to disable it entirely, not just when ACPI mode is disabled. For the situations where this is needed (just the sarien board) it is better to completely stop the EC from sending any SMI events as no actions are taken. Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18mb/google/sarien: Enable BT RkfillLijian Zhao
Add bluetooth Rfkill function to recover the Bluetooth controller in cases where itself has entered a bad state and needs to be recovered. Bug=b:123342945 TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under Bluetooth devices with GPIO in. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f Reviewed-on: https://review.coreboot.org/c/coreboot/+/31765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet ControllerXiang Wang
Initialize the clock of the Gigabit Ethernet Controller. Change-Id: I172dc518c9b48c122289bba5a65beece925410d4 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-03-18mainboard/google/kahlee: Don't use AMD's secure OSMartin Roth
Disable the use of AMD's Secure OS through the Kconfig option. BUG=chromium:903833 TEST=Build google/aleena, verify types 02, 0c, 0d are removed from PSP directory table Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-03-18soc/amd/stoneyridge: Correct PSP SecureOs Kconfig symbolMarshall Dawson
Fix a spelling error in the name. TEST=Build google/aleena and compare amdfw.rom before/after Change-Id: I727ba1d6a8991caa1cdddcfca94c55c73954320a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVPSubrata Banik
This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb File devicetree-override.cb will override required UPDs and is only applicable to CML soc for now Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18mb/intel/coffeelake_rvp: Add cml_u board supportSubrata Banik
This patch adds support to select CMLRVP board. Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18mb/intel/coffeelake_rvp/../cml_u: Do initial mainboard commitSubrata Banik
Clone entirely from mainboard/intel/coffeelake_rvp/../whl_u commit id: 73916defba8d036c2536e1b37a1449ac16e5f56f Change-Id: Icc32a6e1940ba2d13f3ad74cddbb4b75a637cc18 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-17resources: introduce io_resource()Subrata Banik
This patch creates new resource function to perform allocation of IO resource, similar to mmio_resource() function does for MMIO. Change-Id: I3fdcabb14302537d6074bfd6a362690c06b66bb5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-16soc/intel/cannonlake: Add required FSP UPD changes for CMLSubrata Banik
This patch adds required FSP UPD changes for CometLake SoC. Also this patch tries to create common parse logic for CometLake as well as cannonlake SOC. We parse device tree parameters for PCI devices and fill values in FSP UPDs. We fill UPDs based on pci device config as well as SerialIoDev config of devicetree. For PCI devices, if PCI device is disabled from devicetree, we'll assign disable value to FSP UPD. In case devicetree doesn't fill this parameter or value is invalid in SerialIoDev config, default mode will be set to PCI. In case of valid value, we'll fill the same value into FSP UPD. BUG=none BRANCH=none TEST=check if CML board boots and proper UPD values are filled. Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16device/pci_ops: Have only default PCI bus ops availableKyösti Mälkki
In the current state of the tree we do not utilise the mechanism of having per-device overrides for PCI bus ops. This change effectively inlines all PCI config accessors for ramstage as well. Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-03-16device/pci_ops: Reuse romstage PCI config for ramstageKyösti Mälkki
By changing the signatures we do not need to define PCI config accessors separately for ramstage. Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-16src: Drop unused '#include <halt.h>'Elyes HAOUAS
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-16src: Drop unused 'include <device/pciexp.h>'Elyes HAOUAS
Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-03-16drivers/intel/fsp1_0: Deduplicate codePatrick Rudolph
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0. Allows to have a common entry after FSP-M. Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 09:13:13 +0000