summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2012-11-27Add initialization hook for chipsNico Huber
Add an init() function to the chip_operations which will be called before bus enumeration. This allows to disable unused devices before they get enumerated. Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1623 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27Conditionally #include mc1468181rtc if CMOS_POST is enabledDavid Hendricks
This will omit the mc1468181rtc header if it is not needed. Currently it contains a lot of inlined functions which depend on architecture- specific IO. Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1916 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-27Make POST codes written to IO port optionalDavid Hendricks
This adds more configurability to POST codes. The current assumption is that POST codes should be written to an IO port (e.g. LPC) if POST codes are enabled. This changes the assumption so that POST codes can be written to the serial console without being written to an IO port. This enables POST codes by default using "default y" to avoid changing current behavior. Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1685 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24Remove duplicate VGA BIOS interrupt handlersPatrick Georgi
Some boards have two instances of the int15 handler that supports the onboard VGA BIOS, for YABEL and realmode. These are now similar enough that they can be deduplicated. Due to minor differences this requires manual effort. Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
Makes it more similar to what realmode looks like. Change-Id: I4407431f2d979c43dd186114d67ed11845907afe Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Use x86emu register file + definesPatrick Georgi
By using the (global) register file as defined by x86emu, we can use the same register access for YABEL and realmode interrupt handlers. - the x86 realmode interrupt handlers changed in signature - to access registers, use X86_$REGNAME now (eg. X86_EAX) - x86_exception_handler still uses struct eregs *regs to avoid spilling the x86emu register file stuff everywhere Coccinelle script that handled most of this commit: @ inthandler @ identifier FUNC, regs; @@ int FUNC( -struct eregs *regs +void ) { ... } @ depends on inthandler @ identifier regs; @@ -regs->eax +X86_EAX @ depends on inthandler @ identifier regs; @@ -regs->ebx +X86_EBX @ depends on inthandler @ identifier regs; @@ -regs->ecx +X86_ECX @ depends on inthandler @ identifier regs; @@ -regs->edx +X86_EDX @ depends on inthandler @ identifier regs; @@ -regs->esi +X86_ESI @ depends on inthandler @ identifier regs; @@ -regs->edi +X86_EDI @ depends on inthandler @ identifier regs; @@ -regs->eflags +X86_EFLAGS @ depends on inthandler @ identifier regs; @@ -regs->vector +M.x86.intno Change-Id: I60cc2c36646fe4b7f97457b1e297e3df086daa36 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1891 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86 realmode: Adapt to x86emu/YABEL style return codesPatrick Georgi
realmode int handlers must return the same codes as the YABEL int handlers now: 1 for "interrupt handled", 0 for "not handled" (ie. error). Change-Id: Idc01cf64e2c97150fc4643671a0bc4cca2ae6668 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24x86emu: Move realmode handler into own directoryPatrick Georgi
It's really a feature in parallel to YABEL/x86emu. Reflect this in the directory structure. Change-Id: Ie88e4fa6bfef13d23c55b2db3faacbd90f8cc30b Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1889 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-20Persimmon: Disable the unused GPP PCIe clocksDave Frodin
Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-20Unify use of bool config variablesStefan Reinauer
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-20secondary.S: Fix dropping ramstage.aStefan Reinauer
This unused code was not silently dropped as before. Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1863 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20Make sure only one udelay function is availableStefan Reinauer
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions, so don't shove in UDELAY_IO Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1864 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-19siemens/sitemp_g1p1: Drop copy of cmos checksum calculationPatrick Georgi
This code used a special case for checksum calculation to prevent the century byte from messing things up, since writes "sometimes" didn't happen. That should be stable now, so the special case isn't necessary. Downside: On century rollovers (ie. 1999-12-31, 2099-12-31) CMOS will be reset to the defaults. Change-Id: Ibe589a1ec953b7b3ba39be30cebd9fc2b27326ae Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1870 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19bootblock: Guard CMOS rewrite in disable/enable RTCPatrick Georgi
This ensures that there's only one disable/enable cycle for the entire rewrite instead for every single byte. Change-Id: Ic06e6dcb08976d158ff784660838c0fbad875176 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1869 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-19mc146818rtc: disable RTC before writing to nvramPatrick Georgi
In principle this isn't necessary. However there's a byte (or several) outside the first 14 bytes that are part of the RTC, and require locking (century/altCentury). Since their location is mostly unknown, guard writes properly. Change-Id: I847cd4efa92722e8504d29feaf7dbfa5c5244b4e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1868 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-17Drop no-op bootblock.cKyösti Mälkki
Deletes unused file: src/northbridge/amd/agesa/family15tn/bootblock.c Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1843 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17Use new system agent binariesStefan Reinauer
Change-Id: I716564c4ea3b8e298cdeb82dc68e68474ed595cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1879 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Fix PIRQ routing abstractionStefan Reinauer
intel_irq_routing_table is a local structure that should not be used globally, because it might not be there on all mainboards. Instead, the API has to be corrected to allow passing a PIRQ table in where needed. Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Fix Kconfig GENERATE_*_TABLE usageStefan Reinauer
Some boards selected GENERATE_ instead of HAVE_ Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1841 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Clean up KconfigStefan Reinauer
- move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop Kconfig.deprecated_optionsStefan Reinauer
Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET are not likely to go away any time soon, so let's not keep them in Kconfig.deprecated_options but move them close to the code they control. Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1839 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop unused Kconfig variable PCIE_TUNINGStefan Reinauer
It's only mentioned in Kconfig and never set nor used. Change-Id: Icc0ac56ae7b325a9e93ed5cdce9dc4b7bab43140 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1838 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop Kconfig variable BOARD_HAS_HARD_RESETStefan Reinauer
hard_reset was indeed consolidated and moved into the southbridge code a while ago, but the config variable was still kept alife, with some duplicate code. Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1837 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-16Drop unneeded BOARD_HAS_FADT optionStefan Reinauer
Change-Id: Iaaeee87d70cf052bc7980007cdf1f7dda88b3623 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-16Reduce number of per-mainboard changesStefan Reinauer
- Add mainboard_smi.c from arch/x86/Makefile if it's there - Add mainboard's chromeos.c from the chromeos Makefile Change-Id: I3f80e2cb368f88d2a38036895a19f3576dd9553b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1835 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Drop CONFIG_HAVE_BUS_CONFIG, clean up KconfigStefan Reinauer
This patch is the beginning of a Kconfig cleanup series - drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it exists in the mainboard directory - drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig if it only defines the defaul value of 0 - Add mptable.c, fadt.c, reset.c and ssdtX.asl when they exist, not based on some Kconfig magic Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200 Reviewed-on: http://review.coreboot.org/1832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14Use mainboard hook for HP DL165Kyösti Mälkki
The board incorrectly overrides the southbridge hook, so use the new mainboard hook instead. This change also activates the actual southbridge hook to enable decode of complete 4 MB flash memory region. Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14ms9652: fix misuse of LIFT_BSP_APIC_IDStefan Reinauer
It's a bool, not a number Change-Id: I70d52c6af6703101dbd534970ec65275902a283d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1842 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14mainboard/siemens/sitemp_g1p1: Fix YABEL usageNico Huber
The board was broken for use with CONFIG_PCI_OPTION_ROM_RUN_YABEL. Change-Id: Ia57d630143386fe637af83b9e7345d0d3750b089 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Make YABEL's version of mainboard_interrupt_handlers() usableNico Huber
YABEL's version of mainboard_interrupt_handlers() was hidden behind an inline stub. This fixes it. Change-Id: Ie53424a8ce074e93a720c0ef94cb39994cacd023 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14mainboard/siemens/sitemp_g1p1: Fix CMOS checksum algorithm here, tooNico Huber
Some time ago our CMOS checksum algorithm was changed under the topic: Fix our CMOS checksum algorithm so it matches what /dev/nvram expects Here is another copy of the algorithm that had to be updated. Change-Id: I58659c7b8a89c89c76efdff405ee0620e7302277 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Move HAVE_SMI_HANDLER from mainboards to chipsetsStefan Reinauer
Change-Id: Ibb6606fe3996e377181872a4544600f2d58c5439 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1834 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14VIA chipsets: fix compilation without real mode codeStefan Reinauer
The VIA chipsets CX700, VT8623 and VX800 required to be configured with real mode option rom code enabled. This patch fixes the issue and drops some unneeded header files. Change-Id: I0d8a3f8f99c2eacec7666f08f85b99f09c06af84 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1833 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Tell CBMEM code about ACPI GNVS sectionStefan Reinauer
We moved GNVS to it's own section, but forgot to tell the cbmem code about it. This is purely cosmetical, but add it anyways. Change-Id: Icb3788c0325ea79cc1efff4a876412d07da7936e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1782 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Fix save state searching for GSMIDuncan Laurie
The search for save state was comparing the entire RAX value when it needs to just operate on the bottom byte so it can find the GSMI command in bits 7:0 but not the extended command code in bits 15:8. Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1774 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Save the GNVS pointer when creating APCI tablesDuncan Laurie
At boot time when the ACPI tables are created and the location of GNVS is determined then save that address for resume time. This also sets the values of USB charging in S3/S5 to the expected default values for Stout/Butterfly that were not set correctly. Change-Id: I9b94b868aa6e81aced06c0262cc2697ad4faf1e6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1768 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Pass the ACPI GNVS pointer via state save mapDuncan Laurie
Instead of hijacking some random memory addresses to relay the GNVS pointer to SMM we can use EBX register during the write to APM_CNT register when the SMI is triggered. Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1766 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Avoid use of global variables in SMI handlerDuncan Laurie
Using global variables with the TSEG is a bad idea because they are not relocated properly right now. Instead make the variables static and add accessor functions for the rest of SMM to use. At the same time drop the tcg/smi1 pointers as they are not setup or ever used. (the debug output is added back in a subsequent commit) Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1764 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Extract function for finding save state nodeDuncan Laurie
This is currently used by the ELOG GSMI interface but is a good way to pass data to SMM so move the current searching code to a separate function and make it a bit more versatile with the checks it does to find a match so it can be used in other situations. Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14SMM: Restore GNVS pointer in the resume pathDuncan Laurie
The SMM GNVS pointer is normally updated only when the ACPI tables are created, which does not happen in the resume path. In order to restore this pointer it needs to be available at resume time. The method used to locate it at creation time cannot be used again as that magic signature is overwritten with the address itself. So a new CBMEM ID is added to store the 32bit address so it can be found again easily. A new function is defined to save this pointer in CBMEM which needs to be called when the ACPI tables are created in each mainboard when write_acpi_tables() is called. The cpu_index variable had to be renamed due to a conflict when cpu/cpu.h is added for the smm_setup_structures() prototype. Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1765 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Sandybridge: Set PEG clock gatingMarc Jones
If the PEI System Agent doesn't run PCIe initialization, the PEG clock gating will not be setup. Add the PEG clock gating when pei_data->pcie_init is 0. Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add PCIe init and NMode flag to PEI data structureStefan Reinauer
The IvyBridge reference code does some slow and extensive PCIe init that we do not need on Link. Hence, add a flag to disable/enable running that init code from coreboot. NMode was used during bringup. We'll switch the setting back to auto, to let MRC decide the right thing. Change-Id: Ia989bb9ea079aadfeb41dc3029b7c2c623e84760 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Add ddr3lv_support flag to pei_data structureDuncan Laurie
This will enable DDR3 1.35V support for memory training in the reference code. It requires the board to be setup for 1.35V with whatever board-specific GPIOs are available. Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14pei_data.h: Fix commentMarc Jones
I added a comment to the pei_data.h to remind users about how the OC pins are mapped. Change-Id: I4d74eb69fc78816a69e61260c2c9b2b3e58cafec Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1824 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14Provide MRC with a console printing callback functionVadim Bendebury
Let memory initialization code use the coreboot romstage console. This simplifies the code and makes sure that all output is available in /sys/firmware/log. The pei_data structure is modified to allow passing the console output function pointer. Romstage console_tx_byte() is used for this purpose. Change-Id: I722cfcb9ff0cf527c12cb6cac09d77ef17b588e0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1823 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add spinlock to serialize Intel microcode updatesStefan Reinauer
Updating microcode on several threads in a core at once can be harmful. Hence add a spinlock to make sure that does not happen. Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13cros: Inform U-Boot via fake gpio when VGA Option ROM is loadedBill Richardson
This prepares the way for vboot to inform coreboot when it needs the VGA Option ROM loaded. Coreboot can't always know when it's needed (with keyboard-based dev-mode, coreboot can't tell if we're in dev-mode or not). By the time we get to U-Boot, it's too late, so we need two extra bits - one for vboot to tell coreboot to load the Option ROM and another for coreboot to let vboot know it's been done. This change sets up the communication, but doesn't act on it just yet. Even with this CL we always load the VGA Option ROM, so there's nothing to test. There should be no user-visible change. Change-Id: Ic4e9673a3707b6605064f4879bb3e74d4412322f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/1822 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Export optionrom status on Stumpy/LumpyVadim Bendebury
ChromeOS' top of the tree u-boot expects coreboot to export information about option ROM status (started/not started). Stumpy and Lumpy were left behind and are not exporting this information. This CL fixes the problem. Change-Id: Id90035bd76ab177e4fc269efc2b74f15f641c77d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1713 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Make EmeraldLake2 work againDuncan Laurie
Fix GPIO exporting for new Vboot for oprom-matters GPIO and to make the power button static. Change-Id: Ic042c428a1d43512228c686121fa057d876606e1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1761 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 04:02:44 +0000