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AgeCommit message (Expand)Author
2012-11-07AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPUSiyuan Wang
2012-11-07CMOS: Move MRC seed offset into upper bankDuncan Laurie
2012-11-07rtc: force mc146818 register D to a correct valueVincent Palatin
2012-11-07Fix CONFIG_ use in i8254.cStefan Reinauer
2012-11-07Add POST code for "All devices initialized"Stefan Reinauer
2012-11-07Move global variable check to MakefileStefan Reinauer
2012-11-07Leave power control registers unlockedSameer Nanda
2012-11-07Fix whitespace issue with help message in Kconfig fileDave Frodin
2012-11-07AMD rd890 late.c: Don't enable PCIe ports after PCIe init.Siyuan Wang
2012-11-07AMD agesa family15: PCI domain should scan bus from 0x18.0Siyuan Wang
2012-11-06acpi: Add support for DMAR tables (Intel IOMMU support)Patrick Georgi
2012-11-06Drop redundant CHIP_NAME in mainboard.cKyösti Mälkki
2012-11-06smsc/lpc47n227: Make early_serial usablePatrick Georgi
2012-11-06cpu/intel/model_1067x: Add proper c-state/p-state/thermal supportNico Huber
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
2012-11-06Add name field for deviceKyösti Mälkki
2012-11-05Overhaul speedstep codeNico Huber
2012-11-05Fix some indentation flaws and break very long linesNico Huber
2012-11-02remove enable_cache() of 3 mainboardsSiyuan Wang
2012-11-02Persimmon: disable the unconnected Full-Speed USB portDave Frodin
2012-11-02AMD agesa: add enable cache at the end of disable_cache_as_ramSiyuan Wang
2012-11-02Correct FSB reading in speedstep ACPINico Huber
2012-11-02Fix some issues with new "reference" toolchainStefan Reinauer
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
2012-10-30Add support for socket LGA775Stefan Tauner
2012-10-30Fix ExecuteFinalHltInstruction function in f15h family codeKostr
2012-10-30AMD SB800: PCIE slots on PersimmonZheng Bao
2012-10-29Drop get_smbios_data from chip_operationsKyösti Mälkki
2012-10-29Fix reading of number of interrupts for IO-APICsNico Huber
2012-10-29Hide all _ROM_RUN Kconfig options if the payload is SeaBIOSPeter Stuge
2012-10-29Run option ROMs in coreboot by default only if the payload is not SeaBIOSPeter Stuge
2012-10-29Clarify that _ROM_RUN Kconfig options control if ROMs are run by corebootPeter Stuge
2012-10-28IEI PM-LX2-800-R10: Added preliminary mainboard supportRicardo Martins
2012-10-27Take care of NULL chip_ops->nameKyösti Mälkki
2012-10-26iwave/iWRainbowG6: use 16bit access for a register which is not 32bit alignedSebastian Andrzej Siewior
2012-10-26northbridge/sch: move the \n so it reads a little betterSebastian Andrzej Siewior
2012-10-26iwave/iWRainbowG6: remove USE_DCACHE_RAMSebastian Andrzej Siewior
2012-10-26northbridge/sch: read the size of main memory from the proper registerSebastian Andrzej Siewior
2012-10-26northbridge/sch: Read the GPU memory from the correct PCI deviceSebastian Andrzej Siewior
2012-10-26northbridge/sch: don't overwrite hightables with GPU / TSEG memorySebastian Andrzej Siewior
2012-10-24Trinity: Initialize the pointer prior to using itZheng Bao
2012-10-22change conflicted typedef in src/vendorcode/amd/agesa/f15/Porting.hSiyuan Wang
2012-10-16Update SeaBIOS stable to the release-1.7.1 commitPeter Stuge
2012-10-10bachmann/ot200: Fix wrong IRQ number for PIRQDChristian Gmeiner
2012-10-10iei/kino-780am2: Turn on PCIe bridge to 2nd ethernet controller.Dave Frodin
2012-10-08hpet: common ACPI generationPatrick Georgi
2012-10-08Every chip must have chip_operationsKyösti Mälkki
2012-10-07Take care of NULL chip_ops->nameKyösti Mälkki
2012-10-07Fix typo in mPGA603 socketKyösti Mälkki
2012-10-07Remove chip.h files without config structureKyösti Mälkki
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