summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2013-10-17arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOSAndrew Wu
SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify the xcompile script to search for cpp program path, and pass it to SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler). This is needed, so the crossgcc toolchain to build the SeaBIOS payload under Mac OSX. OSX ships a cpp program, but it works differently from GNU CPP, so we need to override it. Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3896 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-15CBMEM: Define cbmem_top() just once for x86Kyösti Mälkki
It is expected this will always be a casted get_top_of_ram() call on x86, no reason to do that under chipset. Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3972 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15Have option of timestamps, CBMEM console and usbdebug for most boardsKyösti Mälkki
As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage, and have no CAR migration, these features are available for ramstage only. Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15CBMEM: Fail builds on missing get_top_of_ram()Kyösti Mälkki
Dummy get_top_of_ram() is removed from romstage to fail already at build-time for cases where cbmem_initialize() would not complete. The mechanisms behind CAR_GLOBAL migration only work correctly when romstage can succesfully make the cbmem_initialize() call. Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3969 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15intel/i82371: Remove HAVE_ACPI_RESUMEKyösti Mälkki
This is needed to apply a rule that get_top_of_ram() in romstage is required to select HAVE_ACPI_RESUME, otherwise chipset/board has no means to backup low memory to CBMEM on s3 resume. Only board affected is asus/p2b. Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3971 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15timestamps: Fix some lost timestamps for romstageKyösti Mälkki
Timestamps from cbfs_and_run, TS_START_COPYRAM and TS_END_COPYRAM, were lost with commit b766b1c7. Reason is variable ts_table was referencing CAR storage after CAR is torn doesn. Add use of car_get_var() / car_set_var() so the references go to migrated storage in CBMEM. Change-Id: I5a942ad7fd59a04e3a5255f4a3636d37dcfc1591 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with UbuntuWANG Siyuan
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary Linux Display Driver[1]. [1]. http://support.amd.com/us/gpudownload/linux/Pages/radeon_linux.aspx Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3934 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-10-15ASRock IMB_A180: fix Ubuntu HDMI audio issueWANG Siyuan
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. I have tested on Ubuntu 13.04 with latest graphic driver. Change-Id: I09c19b8925eedee03cfb1d8c0831a84e8aeeba4f Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3937 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-10-15AMD Olive Hill: fix Windows 7 HDMI audio issueWANG Siyuan
Windows 7 cannot find HDMI audio device because of acpi setting. I have tested on Windows 7. I can play music. Change-Id: I90ade7e7be79f65783922333c2cbb2d3cc6557ea Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-15vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7WANG Siyuan
The platform initialization (PI) code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. Use the name Kabini instead of Kerala everywhere. Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0 as used in `AGESA_VERSION_STRING`. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3935 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-14Revert "CBMEM: Always have early initialisation"Kyösti Mälkki
This reverts commit de1fe7f655c549e8dce5b34218221890fa5ccc34. While things appeared to work, there were actually invalid references to CAR storage after CAR was torn down on boards without EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be restricted to boards that handle CAR migration properly. Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1Jonathan A. Kollasch
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is 0xfec00000 (that is, outside the range of bus 0 address space). This causes IOAPIC interrupts to fail to work under Linux. This issue was originally unnoticed by me when testing as sanity checking such as this is not done by NetBSD. Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've checked. Change-Id: I736db163750f709d68c988fac075597a50b29ab7 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3963 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14ck804: obtain stored IOAPIC address from allocator instead of registerJonathan A. Kollasch
Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3961 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14ck804: obtain I/O APIC base address for ACPI MADT from allocatorJonathan A. Kollasch
Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3960 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13dmp/vortex86ex: Initialize PS/2 keyboard.Andrew Wu
Call pc_keyboard_init function in southbridge. It makes PS/2 keyboard work in coreinfo payload. Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3957 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in ↵Paul Menzel
`setup_mtrr_dqs()` Change-Id: I7fc7819c329c058472031e82237be5c170b277f4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3965 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-13ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14Jonathan A. Kollasch
Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3962 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-10-12Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt ↵Jonathan A. Kollasch
routing initialization Change-Id: I6cb4ad5ea5ad40284f8e88ff440f2605d3b83359 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-10-07AMD hudson yangtze: Fix corruption of a global ramstage variableKyösti Mälkki
A late for loop may reference over the current array allocation and corrupt an unrelated global variable. As a quick fix bumb the size of the array allocation uniformly to 6. We missed these boards for commit 9c7d73ca because the arrays had been renamed. Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3954 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-03cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`Paul Menzel
When building coreboot with the Clang static analyzer scan-build, it reports »Value stored to 'type_index' is never read«. Indeed, in `memranges_each_entry()` `type_index` is assigned a value before being read. So remove that line. Change-Id: I6da2fb8be7157bb98c57281babd4a08ca0d9f7a7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-01qemu: q35: avoid address conflictGerd Hoffmann
Qemu has the fw_cfg interface at 0x510, which conflicts with power management base address in coreboot. Move the pmbase to a non-conflicting address. No need to worry about speedstep, it is not supported by qemu and isn't enabled in the qemu config. Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-28exynos5420: Fix build warningAllen Martin
Fix "set but not used" variable warning with gcc 4.7.3 Change-Id: Ia27291ecb4f993c4ba6f29b134167dc23a449bf5 Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-on: http://review.coreboot.org/3949 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-09-27ASRock IMB_A180: fix Windows 7 HDMI audio issueWANG Siyuan
Windows 7 cannot find HDMI audio device because of acpi setting. I have tested on Windows 7. I can play music. Change-Id: I53177ce00b676824a903a3397d69338e8c1a38af Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-25usbdebug AMD: Add choice of EHCI controllerKyösti Mälkki
Chipsets sb700 and sb800/hudson have more than one USB EHCI controller, implement the selection logic using already existing Kconfig option. Change-Id: I9e0df1669d73863c95c36a3a7fee40d58f6f097e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3928 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-21CBMEM: Always select CAR_MIGRATIONKyösti Mälkki
If romstage does not make cbmem_initialize() call, linker should optimize the code for CAR migration away. This simplifies design of CBMEM console by a considerable amount. As console buffer is now migrated within cbmem_initialize() call there is no longer need for cbmemc_reinit() call made at end of romstage. Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21CBMEM: Always have early initialisationKyösti Mälkki
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig. If romstage does not make the cbmem_initialize() call, features like COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during romstage, but that data will get lost as no CAR migration is executed. Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3917 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21ROMCC boards: Fix builds with CBMEM console, timestamps or usbdebugKyösti Mälkki
These features depend on CAR_GLOBAL region, which is not available when romstage is built with ROMCC. Exclude these from romstage, keep them available for ramstage. A follow-up patch will fix the dependencies and allows enabling these features in menuconfig. Change-Id: I9de5ad41ea733655a3fbdc734646f818e39cc471 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21CBMEM console: Support late initKyösti Mälkki
It is not compulsory to have CBMEM console initialised in romstage, so try add the CBMEM table entry again in ramstage, if not found. Change-Id: I96ab502df7f05d6bf1d6e6fa84d395ef6306b525 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3915 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Only collect from BSP CPUKyösti Mälkki
We only have one table to collect timestamps into. Change-Id: I80180fe9a05226f0351c3e66eacaf2d0cb82c924 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3912 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps epia-m850: Cleanup without enabling timestampsKyösti Mälkki
Remove the existing hack, platform needs a fix for EARLY_CBMEM_INIT. Change-Id: I7ce373c9698878d9fa056983e4fb571a68239c52 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3913 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Stash early timestamps in CAR_GLOBALKyösti Mälkki
Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3910 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps: Use stash before CBMEM is usableKyösti Mälkki
Change-Id: I9e927abdb1d7d9c233de5620a9a65b419e803ebf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21timestamps intel: Move timestamp scratchpad to chipsetKyösti Mälkki
This retrieves back the value stored with store_initial_timestamp() in the bootblock for southbridge. Change-Id: I377c823706c33ed65af023d20d2e4323edd31199 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3908 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-20usbdebug: Allow an USB hub on the debug dongleKyösti Mälkki
Some development kits with USB 2.0 HS OTG have an USB hub instead of being directly connected to the USB host/device controller. Send the necessary initialisation sequence, using HUB CLASS requests of PORT_POWER and PORT_RESET to enable a pre-selected port number where a device supporting debug descriptor is located. This also adds the Kconfig option for BeagleBone. Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3925 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-19ASUS F2A85-M: Correct and clean up PCIe configRudolf Marek
Assign the lanes correctly to the physical slots on the motherboard in `PlatformGnbPcie.c`. • UMI is connected to SB via 4x PCIe bridge 8. • The blue x16 slot is not shared with DDI and is routed through PCIe bridge 2. • The black x8 slot is in fact a x4 slot and uses all 4 GPPs from the CPU. • Assume that DDI is on out-of-PCIe-band lanes. Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3194 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-09-18qemu: q35: fix pci bar placementGerd Hoffmann
Without this coreboot may (depends on the amount of memory) place the pci bars below 0xb0000000, then the linux kernel goes move them around so they are inside the window declared in the acpi tables. This breaks vesafb as the vga framebuffer gets moved after vgabios initialization. It's also not exactly nice to expect the OS fix our mess ;) Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3927 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-17Fix whitespace leaked into treeKyösti Mälkki
Clean whitespace errors that have gotten past lint-stable-003-whitespace and gerrit review. Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3920 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17beaglebone: Stop reinitializing the console in bootblock.c.Gabe Black
The console has already been initialized in the generic bootblock code, and reinitializing it causes the same banner line to be printed twice and lots of artifacts in the actual output. This same change had been made to the other ARM boards but not for beaglebone. Change-Id: I72e3be1326b1a52b7ec438a44e4fd5f87e4ec717 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3924 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-17ARM: Add some missing dependencies on config.h to ARM's Makefile.inc.Gabe Black
These dependencies came indirectly through kconfig.h which was included automatically with a -include option which was either part of INCLUDES or specified directly. With this change, I'm able to build for beaglebone with make -j 48. Change-Id: Ib57d0c6a755b747165b235c2328c3c30bd6dd67d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3922 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-17am335x: Update the config vars selected by CPU_TI_AM335X.Gabe Black
The way those variables work has changed twice since this file was last changed, and console output was no longer working. Now that they're up to date there's serial output from beaglebone again. Change-Id: I5167fd8c0a8c33438d7f056fdf5951bd054010ed Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-11CBMEM: Rename high_tables variables and make them staticKyösti Mälkki
Old name was too much x86. All external references have been removed. Change-Id: I982b9abfcee57a7ea421c245dadb84342949efae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3906 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Drop parameters from cbmem_init()Kyösti Mälkki
The parameters can be dropped as initialisation always happens for the region resolved with cbmem_locate_table(). This is no longer referenced externally, make it static. Change-Id: Ia40350a5232dcbf30aca7b5998e7995114c44551 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Drop parameter from cbmem_reinit()Kyösti Mälkki
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE which equals cbmem_base, thus no need to pass it as a parameter. Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM ARM: Prefer get_cbmem_table() over cbmem_late_set_table()Kyösti Mälkki
Implementing get_cbmem_table() allows initializing CBMEM earlier. Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3560 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM x86: Unify get_cbmem_toc()Kyösti Mälkki
Remove any chipset-specific implementations and use arch-specific implementation of get_cbmem_table() instead. Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3907 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Backup top_of_ram instead of cbmem_tocKyösti Mälkki
AMD northbridges have a complex way to resolve top_of_ram. Once it is resolved, it is stored in NVRAM to be used on resume. TODO: Redesign these get_top_of_ram() functions from scratch. Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Add cbmem_locate_table()Kyösti Mälkki
For both romstage and ramstage, this calls an arch-specific function get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage, the result is cached as the query may be relatively slow involving multiple PCI configuration reads. For x86 CBMEM tables are located right below top of low ram and have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation. Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11CBMEM: Unify get_top_of_ram()Kyösti Mälkki
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 01:51:43 +0000