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2021-01-18mb/ocp/tiogapass/ramstage.c: Remove duplicated includeElyes HAOUAS
Change-Id: I6549ad6704c62b968ff9eb59cc698107c0120fb8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18security/intel/stm/StmPlatformSmm.c: Remove repeated wordElyes HAOUAS
Change-Id: I45adc4622f2d3358c703259931bafc4511395a5a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18northbridge/intel/x4x/dq_dqs.c: Remove repeated wordElyes HAOUAS
Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18soc/intel/xeon_sp/uncore.c: Remove duplicated includeElyes HAOUAS
Change-Id: I2ac1035585b32ba65d0725067cff0c12c9f748c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/intel/xeon_sp/skx/soc_acpi.c: Remove duplicated includeElyes HAOUAS
Change-Id: Icf4247a0a5fb7950c69c8f229a6629a4fa6980f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18drivers/maxim/max77686/max77686.h: Remove repeated wordElyes HAOUAS
Change-Id: Iac77f401d80027231f8b6a3449cb57abf3d337ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18lib/device_tree.c: Remove repeated wordElyes HAOUAS
Change-Id: Id5279587231c539bd3ffc75b75b29d88ef30e56a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/amd/stoneyridge/romstage.c: Remove repeated wordElyes HAOUAS
Change-Id: I38974b532f41830f49b54444d98e6bd7aa417aba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18northbridge/intel/gm45/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: Ie3bfdb27aa7c981a500e82b6a6958576e0048bcd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18ec/google/chromeec/ec_commands.h: Remove repeated wordElyes HAOUAS
Change-Id: I87d5a5fa584b4250bc8b532c046e6bd070e33e81 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18northbridge/intel/x4x/raminit_ddr23.c: Remove repeated wordElyes HAOUAS
Change-Id: I9763499ad5cf0395c83770908a277f089ceed475 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18include/edid.h: Remove repeated wordElyes HAOUAS
Change-Id: Ia6dfc89e575e1a47f980a008ae7334fc21afde89 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18security/vboot/secdata_tpm.c: Remove repeated wordElyes HAOUAS
Change-Id: Idc17a4305398defd19e7f6ba2fc00bf69af34c4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18northbridge/intel/sandybridge/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: I9e723e1d31b093a4781413efe7f290a295b833dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18include/memrange.h: Remove repeated wordElyes HAOUAS
Change-Id: Id010c72bbbb302f1756a53a228fa0bdd7ec7654b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/broadwell/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: I3aec07d782e4315120a4365a65bdbcbf4a22e6f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/common/block/include/intelblocks/pmc_ipc.h: Remove repeated wordElyes HAOUAS
Change-Id: I646583f7f0d0e0f6a91bc99b7edda964337d837e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/common/block/itss/itss.c: Remove repeated wordElyes HAOUAS
Change-Id: Icc4954bcc1540f1935b0e34107febb4a1e947a36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/skylake/chip.h: Remove repeated wordElyes HAOUAS
Change-Id: Id5bf9255e9a16a4f311e3b15eb77ad6e4bb13f66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/nvidia/tegra124/spi.c: Remove repeated wordElyes HAOUAS
Change-Id: I0018ea16f304a0d2cedfbd55525ecabbf2d89aa1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/nvidia/tegra210/spi.c: Remove repeated wordElyes HAOUAS
Change-Id: Iea0c973b2bd493eb69ef76289b5b4fc66ac622f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18ec/google/chromeec/ec.h: Remove repeated wordElyes HAOUAS
Change-Id: I7f567f2b4c582e4b2bb102ef0e0f68c5bf6cfb9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18drivers/intel/gma/intel_bios.h: Remove repeated wordElyes HAOUAS
Change-Id: I5866a5e3240e49119e29f728202b33dd82ceaf77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18device/xhci.c: Remove repeated wordElyes HAOUAS
Change-Id: Ia1648bd7ba4858268ca5f1a5c7b42b7de717d3d6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18device/pci_device.c: Remove repeated wordElyes HAOUAS
Change-Id: Ia6936675684e3eaf2a57e2d28e465b1f0768249b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18cpu/x86/smm/smm_module_loaderv2.c: Remove repeated wordElyes HAOUAS
Change-Id: I712fca09b1618017412a3d91f81627ec876f2894 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18cpu/x86/mtrr/earlymtrr.c: Remove repeated wordElyes HAOUAS
Change-Id: I7e7570ff6a4319a0cf583ae5b76e7c24f0241509 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18cpu/intel/smm/gen1/smmrelocate.c: Remove repeated wordElyes HAOUAS
Change-Id: I478f8ab0cf0a4004b4d7294efb330dc800253e4a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18nb/intel/gm45/gm45.h: Remove duplicated includeElyes HAOUAS
Change-Id: Iabd6c69cd4c28f0015d4cf1f95d5ae0b6dc8b47e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/amd/common/block/smi/smi_util.c: Remove repeated wordElyes HAOUAS
Change-Id: Ifeac919ac7214c1baf877a36fd3d57636fc83563 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-18soc/intel/alderlake: Update PCH and CPU PCIe RP tableEric Lai
According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18soc/intel/common: Move L1_substates_control to pcie_rp.hEric Lai
L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18mb/purism/librem_cnl: Update HDA verbs for Librem MiniMatt DeVillier
Disable all NIDs other than those for the front combo jack. Adjust attributes to match jack physical location, appearance, etc. Correct group number for verbs for HDMI output. Test: run hdajackretask, verify NID characteristics correct for each verb. Verify headphone detection and output functional. Change-Id: If9fca5d9795d56bd38c8ea47f8de985c14ac8fab Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49464 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguousFurquan Shaikh
In case of CPU PCIe RPs, the RP numbers might not be contiguous for all the functions in a slot. Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as per the FSP expectations. Hence, this change updates the defintion of `struct pcie_rp_group` to include a `start` member which indicates the starting PCI function number within the group. All common functions for PCIe RP are accordingly updated to take the `start` member into account. Thus, in the above example, ADL can provide a cpu_rp_table as follows: { { .slot = PCIE_SLOT_6, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_1, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_6, .start = 2, .count = 1 }, } Since start defaults to 0 when uninitialized, current PCH RP group tables don't need to be updated. Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ec/system76/ec: Add fan and temperature reportingJeremy Soller
Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Change-Id: Iee19e7518ffaacd9a847cb6d28c839d4ec464514 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18lib/ramtest: Fix ram_check() declarationsKyösti Mälkki
For a long time, second parameter 'stop' has been ignored. The tested range is within 1 MiB above 'start'. Change-Id: Icbf94cd6a651fbf0cd9aab97eb11f9b03f0c3c31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48561 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/dedede/var/sasuke: Disable PCIE RP8 and CLKSRC3Seunghwan Kim
This change disables unused PCIE RP8 and CLKSRC3. Without this change sasuke cannot enter into s0ix properly. BUG=b:176862270 TEST=Built and verified entering s0ix Change-Id: I0828813ed7924669cb0ff97be2565579762c810f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49300 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/dedede/var/sasuke: Add USB2 PHY parametersSeunghwan Kim
This change adds fine-tuned USB2 PHY parameters for sasuke. BUG=176060155 TEST=Built and verified USB2 eye diagram test result Change-Id: Id374ed238d92077ca28c1162fd9f070029ee71bd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49321 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18mb/google/volteer/var/elemi: Configure USB2 portsWisley Chen
Configure the USB2 port 3/4/9 1. USB2 port3 assign to WWAN, and elemi have no WWAN. 2. USB2 port4/port9 connect to Type-C C1/C0 BUG=b:177483059 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I9affc69cc325b5eb0219b50bfe46f66eb0bb2016 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49473 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18drivers/i2c/sx9324: Add IrqCfg1 registerStanley Wu
Add IrqCfg1 register for proximity IRQ function and polarity setting. BUG=b:175932166 BRANCH=dedede TEST=Build passed. Change-Id: I3cee84a5658fecf55d2d8b8621879588ffe0158d Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49220 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ChromeOS: Refactor SMBIOS type0 bios_version()Kyösti Mälkki
Pointer to an empty string (filled with spaces) is stored inside GNVS. Rearrange things to avoid having <chromeos/gnvs.h> in SMBIOS code. Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49281 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-16mb/google/volteer: do UART pad config at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I5e07584d7857052c7a9388331a475f5a073af038 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-16mb/system76/lemp9: do early pad configuration in early bootstageMichael Niewöhner
Do early pad configuration in early bootblock before console init, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Ie122a441145383b820d96e32ce1581dfc27fa57b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15mb/amd/mandolin: Clean up IRQ numbersRaul E Rangel
We no longer need the IO-APIC assignments since we use the GNB IO-APIC. We were also missing the E-H IRQ mapping. I also renumbered them since IRQ 8 is used by the rtc. TEST=none BRANCH=zork Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia956ae457669aeda6fa49e127373aad3807f7b9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15mb/google/zork: update USB 2.0 controller Lane Parameter for dirinbozKevin Chiu
Enhance USB 2.0 M/B C0, DB C1 A1 port: HS DC Voltage Level(TXVREFTUNE0): 0xe COMPDISTUNE(COMPDISTUNE0): 0x7 BUG=b:165209698 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I371e4295c2ee161096f0a277c0c649bf217269b2 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-15mb/google/zork/var/shuboz: update STAPM add telemetry settingKane Chen
1. Modify STAPM time constant 2500 to 1400. 2. Add telemetry setting: VDD Slope : 30518 VDD Offset: 435 SOC Slope : 22965 SOC Offset: 165 BUG=b:177399751 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I251029389c10ee0f17f368b1c00ac666d372fc3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-15mb/google/zork: update DRAM table for berknipKevin Chiu
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id BUG=b:176313722 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ia1947fa158a1113c4a0b1a0d55f657ddaac43382 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-16 14:12:21 +0000