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2018-04-29mainboard/gigabyte/ga_2761gxdk: Remove unnecessary braces {}Elyes HAOUAS
Fix coding style Change-Id: Id1c7104eb8520f20c826f5936029739a093d4dba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-29sb/broadcom/bcm5785/early_setup.c: Fix coding styleElyes HAOUAS
Change-Id: Ic8218078f4b1075b41f769e26e34adf9c9b113ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-29southbridge/nvidia: Remove spaces before/after parenthesisElyes HAOUAS
Change-Id: I94a87d631c9336b861523592ff217fe823436b36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-28nb/intel/x4x: Fix computing page_sizeArthur Heymans
This variable needs to be in byte so a division by 8 needs to happen. This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD decode and timing selection", but was probably not encountered because such dimms are rather uncommon. Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22991 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-28src/southbridge/sis/sis966/nic.c: Improve code formattingElyes HAOUAS
Change-Id: If4f3d3ed43fca1bff52ea99cc3eab29beb4e2a08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-28src/console: Add spaces around '=='Elyes HAOUAS
Change-Id: I61ff3adb573ffc99f37a1cdcbf5d0d83b2dec0ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25854 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-28src/southbridge: Add spaces around '=='Elyes HAOUAS
Change-Id: Ic81601cef841076a7548ccb3bdf0ed1b5420873e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-28mainboard/asus: Add spaces around '=='Elyes HAOUAS
Change-Id: I559e71ddc71115167ea4fa380c3c48ac68154f86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25855 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-28arch/x86: Fix call for wait_other_cpus_stop()Kyösti Mälkki
Fix regression after commit 0cc2ce4 arch/x86: Clean up CONFIG_SMP and MAX_CPUS test In case PARALLEL_CPU_INIT=y BSP CPU no longer waited for APs to stop before proceeding to next bootstates or device initialization. Change-Id: Ie47e7896ed3d57d98a3ce6766e5c37b6dc22523b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/25874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-28nb/intel/i945/gma: Skip native VGA init for ACPI S3 resumePaul Menzel
Currently, native VGA initialization takes 90 ms during resume. But, it is not needed. So, skip it to save that time. Note, it is assumed that ACPI aware operating systems ship the appropriate drivers to initialize the graphics device. With Linux, if the module/driver *i915* is not loaded, then the display will stay black. TEST=On Lenovo X60t with Debian and Linux 4.15.11-1~bpo9+1, suspend and resume system and notice display is correctly initialized by the driver i915 after resume. Notice the messages below. ``` PCI: 00:02.0 init ... Skipping native VGA initialization when resuming from ACPI S3. PCI: 00:02.0 init finished in 56 usecs PCI: 00:02.1 init ... ``` Change-Id: I6cc9dde94c18671d077132daf648e8ba557e7887 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/25676 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-28nb/intel/i945/gma: Factor out code to new `gma_ngi()`Paul Menzel
This helps with meeting the line length limit. Also, join some lines with the one above, as the line length is now met. Change-Id: If457b3b592211aba1a3218501146b17abb5b799f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-28mb/google/octopus: Enable pull on ESPI_IO1 lineFurquan Shaikh
This change configures a weak internal pull-up on ESPI_IO1 line for octopus baseboard and variant bip. ESPI_IO1 is used as ALERT# line and is expected to be open-drain. However, there is no external pull on this line and so an internal pull-up is required to ensure proper eSPI communication. BUG=b:78497502 TEST=Verified that there is no eSPI communication failure between AP and EC during boot-up and on suspend/resume. Change-Id: Ic494aa7397b94bfd233ce10da8287660997b3377 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-04-27soc/intel/apollolake: enable cache-as-ram paging for glkAaron Durbin
Add support and enalbe cache-as-ram paging for glk to work around a cache-as-ram corruption issue. glk executes verstage, romstage, and FSP-M directly out of cache-as-ram (just like apl). However, the front end on glk is very agressive about pulling cache lines into L1I for potential execution. When the snoops hit in the L1D and the cache lines are dirty the processor writes the line back. However, there is no backing store for the dirty lines to go. As such when the line is pulled back in the value is all 0xff's, corrupting cache-as-ram. To fix the issue one needs to enable paging with NX (no execute) permissions which prevents the above actions from happening because the TLB will indicate that shouldn't be fetched into the instruction cache since data will be marked no execute. The generated page tables are added to cbfs and only added to the COREBOOT cbfs as they are only consumed in the early cache-as-ram stages. The page tables generated with: $ go run util/x86/x86_page_tables.go \ --iomap_file=src/soc/intel/apollolake/glk_page_map.txt \ --metadata_base_address=0xfef00000 \ --pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \ --pt_output_c_file=src/soc/intel/apollolake/pt.c Merged address space: 00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small 00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small 00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small 00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small 00000000ff000000 -- 0000000100000000 WP : 8 big 0 small Total Pages of page tables: 5 Pages linked using base address of 0xfef00000. BUG=b:72728953 Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-27drivers/usb: Add spaces around '=='Elyes HAOUAS
Change-Id: If72ce868cdd06183e5055deb94b9d0cf12ed8738 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25858 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27drivers/i2c/lm63: Remove unneeded headersElyes HAOUAS
Change-Id: Id13eef7f0fca0b929372490859aa4734ea7a9f23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27drivers/i2c/adm1026: Remove unneeded headersElyes HAOUAS
Change-Id: Iaed9c0882847511642d8eaab25e10d1ecf24bf90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27drivers/i2c/adm1027: Remove unneeded headersElyes HAOUAS
Change-Id: I147b3a2c79cd5e6b0e5fa3d23221a6afda8ba8f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27soc/amd/stoneyridge/include/soc/smi.h: Fix name collisionRichard Spiegel
When smi.h is included to southbridge.h (to use SCI/SMI definitions within southbridge.h definitions), this causes a collision of the definition of NONE (ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt types (SCI/SMI), add INTERRUPT_ at the start of each definition. This is preparation to have GPIO table/code also declare/program SCI/SMI. BUG=b:72875858 TEST=Build grunt. Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25845 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
The following things are specific characteristic of mc_apl1 board variant: - initialization for the eDP to LVDS converter - enable decoding address range for COM 3 - legacy IRQ routing for PCI devices - wait function for old legacy devices - set coreboot ready LED Change-Id: I5c853e6caae6cc880ead436f232cabddeee6d09a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/25822 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27drivers/asmedia: Add ASPM blacklistNico Huber
To be selected by mainboard Kconfig if the board hosts an ASMedia chip that spuriously advertises ASPM features. Change-Id: I05f9789bc14db56d2ac085f4f14047d80c3aefb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25619 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27google/kahlee: Remove VBOOT_VBNV_CMOSMarc Jones
Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the stoneyridge Kconfig. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27google/kahlee: Add RW_NVRAM to FMAPMarc Jones
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-27soc/amd/stoneyridge: Enable CMOS VBNV backup to flashMarc Jones
Now that we have SPI flash writes working, we can support VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve the area in FMAP. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25842 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27mb/lenovo/x1_carbon_gen1/spd: remove trailing whitespaceElyes HAOUAS
Change-Id: Ic81a172cdeb6c0dca396312393897613c1c51191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27mb/pcengines/apu2/spd: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I0c59cefa4067d3fc01b8425184e10d3caf1c81ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27RISC-V boards: Remove PAGETABLES section from memlayout.ldJonathan Neuschäfer
RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-27drivers/uart: Allow the 8250IO driver only on x86Jonathan Neuschäfer
The driver relies on I/O space access functions (inb, etc.), which are only available on x86. Rather than explicitly disallowing it on ARM, allow it only on x86. TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not available in the "Generic Drivers" menu anymore. Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-27vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.2 for Gemimilake CQ-DEPEND=CL:*594651,CL:*598345 Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-27mb/google/poppy,soraka,nautilus: Enable xDCIFurquan Shaikh
This change enables xDCI controller on poppy, nautilus and soraka. BUG=b:78577893 BRANCH=poppy Change-Id: I9b0f81bda889b822479ead4d1acc2b613151a304 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25849 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27soc/intel/common/block/xdci: Use vboot_can_enable_udc in xdci_can_enableFurquan Shaikh
This change uses the newly added vboot_can_enable_udc to decide if it is okay to enable xDCI in vboot developer mode. BUG=b:78577893 BRANCH=poppy Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27security/vboot: Add function to check if UDC can be enabledFurquan Shaikh
Add a function that will check the various requirements to enable USB Device Controller (UDC): - developer mode enabled - GBB flag set or VBNV flag set If VBOOT is not enabled, then default is to allow UDC enabling. BUG=b:78577893 BRANCH=poppy Change-Id: Id146ac1065f209865372aeb423f66ae734702954 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25847 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27security/vboot: Add function to read UDC enable flagFurquan Shaikh
This change adds a helper function to read USB Device Controller (UDC) enable flag from VBNV. BUG=b:78577893 BRANCH=poppy Change-Id: Ifd1e9b0781ffee242d695b72287632bc944a50c7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-26mainboard/google/kahlee: Set SPI speed in bootblockMarc Jones
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock. This setup is needed when moving AGESA out of the bootblock. It sets the SPI bus speed of the TPM access in verstage. BUG=b:70558952 TEST=Boot with AGESA moved out of the bootblock. Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26soc/amd/common/block/include/amdblocks/psp.h: Replace todo messageRichard Spiegel
It was decided to not add the buffers definitions, so the todo message is obsolete. Replace it with minimum instructions about when a new buffer will be needed. It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO. BUG=b:77940747 TEST=None. Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25740 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26src: Fix a typo on "mtrr"Elyes HAOUAS
Change "mttrs" to mtrrs. Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26device: Add flag to disable PCIe ASPMNico Huber
For broken devices that spuriously advertise ASPM, make it possible to decide ASPM activation in the device driver. Change-Id: I491aa32a3ec954be87a474478609f0f3971d0fdf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25617 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mb/google/octopus: Add dptf.asl in dsdt.aslSumeet Pawnikar
This patch enables dptf for Octopus by adding dptf.asl in dsdt.asl. BUG=b:74263914 BRANCH=None TEST=None Change-Id: I7194cdd2af88ff062ebcc92cc97b3cdc3d21ecd6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-26mb/google/grunt: Add grunt touchpad wake GPE to devicestreeDaniel Kurtz
The grunt touchpad interrupt can be used as a wake source. For grunt, the touchpad interrupt uses GPIO5 which corresponds to GEVENT7. BUG=b:77602771 TEST=In OS: # cat /proc/acpi/wakeup => D015 S3 *enabled i2c:i2c-ELAN0000:00 TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3. Change-Id: I510642108a1257f6601f18c77cf3107573427f39 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25827 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mainboard/google/kahlee: Enable EC wake on GPIO24Daniel Kurtz
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO24 maps to GEVENT (GPE) 15. The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP. On Stoney, GPIO2 maps to GEVENT (GPE) 8. BUG=b:78461678 TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3. TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3. Change-Id: Ib1809740837e686992ff70b81933159a5dff7595 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mainboard/google/kahlee: Fix EC_SMI_GPIDaniel Kurtz
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI definition format a bit to match the format in the baseboard/gpio.h. BUG=b:78461678 TEST=build coreboot for kahlee Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-04-26mb/lenovo/x200: Use acpi_s3_resume_allowed()Paul Menzel
Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed()) also to the Lenovo X200. Change-Id: I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/25793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-26soc/intel/apollolake: enable exception handling in every stage for glkAaron Durbin
Now that an idt is available in every stage utilize it for exception processing to help catch and debug issues. BUG=b:72728953 Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: remove nop padding from exception vectorsAaron Durbin
Now that assembly code isn't processing the idt gates there's no need to ensure each vector entry is the same amount of code. BUG=b:72728953 Change-Id: I2b248b26b9df36d6543163762c74622f79278961 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25765 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: print cr2 value on every exceptionAaron Durbin
Even though most x86 systems don't run with paging on, it's helpful to always print it out for the ones that do without making a more complicated handler. New dump will look like the following: Unexpected Exception: 6 @ 10:7ab84be2 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 7abb80ec ebx: deadbeef ecx: 00000000 edx: 00000002 edi: 7abb3000 esi: 00000004 ebp: 7abb2fd8 esp: 7abb2fb0 7ab84ba0: 00 01 00 83 ec 0c 6a 39 7ab84ba8: e8 8a 02 01 00 e8 e1 08 7ab84bb0: 00 00 e8 4e 3d 00 00 59 7ab84bb8: 5b 52 50 e8 f5 3c 00 00 7ab84bc0: c7 04 24 0a 00 00 00 e8 7ab84bc8: 3c 3d 00 00 c7 04 24 80 7ab84bd0: 00 00 00 e8 5f 02 01 00 7ab84bd8: e8 1e 38 01 00 e8 7e 50 7ab84be0: 01 00 0f 0b bb 98 ec ba 7ab84be8: 7a 83 c4 10 8b 03 85 c0 7ab84bf0: 0f 84 be 00 00 00 83 78 7ab84bf8: 04 00 8d 50 08 75 0c 56 7ab84c00: 56 ff 30 52 e8 f8 fe ff 7ab84c08: ff eb 0a 51 51 ff 30 52 7ab84c10: e8 2e ff ff ff 83 c4 10 7ab84c18: 83 c3 04 eb cf 89 d8 e8 BUG=b:72728953 Change-Id: I0e87bbe776f77623ad8297f5d80167998daec6ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25762 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26arch/x86: allow idt to be available to link in all stagesAaron Durbin
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having the interrupt handling code available to all stages. In order to do this the idt setup is moved to a C module. The vecX entries are made global so that a table of references to all the interrupt vector entry points can be used to dynamically initialize the idt. The ramification for ramstage is that exceptions are initialized later (lib/hardwaremain.c). Not all stages initialize exceptions when this Kconfig variable is selected, but bootblock for the C, stages using assembly_entry.S, and of course ramstage do. Anything left out just needs a call to exception_init() at the right location. BUG=b:72728953 Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-26drivers/i2c/ck505: Remove unneeded headersElyes HAOUAS
Change-Id: Ic525c92e73097752a7c690186dc2034785cac678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25821 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26mb/sifive: Add HiFive Unleashed mainboardJonathan Neuschäfer
Change-Id: I52ef2da9148809923c90178a00ba94babba8d2f8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26src/sifive: Add the SiFive Freedom Unleashed 540 SoCJonathan Neuschäfer
The FU540 is the first RISC-V SoC with the necessary resources to run Linux (an external memory interface, MMU, etc). More information is available on SiFive's website: https://www.sifive.com/products/hifive-unleashed/ Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26arch/riscv: Store mprv bit in size_tJonathan Neuschäfer
CSRs are XLEN bits wide (i.e. the same width as general purpose registers), so size_t seems a little more correct than int. This change doesn't affect functionality because MSTATUS_MPRV already fits in 31 bits. Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26soc/amd/stoneyridge: Fix smi_write32 arg order in disable_all_smi_statusDaniel Kurtz
The argument order for smi_write32() is offset, value. Current code had it backwards. So, when disable_all_smi_status() was called by sb_slp_typ_handler(), instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2 by writing 0x00000002 to 0xfed80288, it would instead write 0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04 Event_Enable, which disabled the lower 16 GPEs from waking the system from S3. Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7] did not work as wake up sources. BUG=b:78461678 TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3. Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46 Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler") Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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