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ACPI aware OS will need _PRT table to get desired interrupt
resource assigned and make device driver working. The logical
device within SOC gets fixed interrupt line.
Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14243
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add southbridge and LPSS device DSDT table.
Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14218
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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HPET table is required to report integrated HPET timer to kernel.
Without HPET table added,Linux kernel will panic when loading timer
driver.
Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13374
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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A dedicated pci device driver required for LPC devices as the legacy
IO range need to be included to avoid IO resource confilict. Blindly
set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD
and LPC.Without this driver system will have assertion on load
RTC DXE driver in UEFI payloads.
Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13356
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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ACPI MADT tables required to describe the multiprocessor interrupt
routing. Apollolake SOC also have the interrupt override table like
other x86 silicons.
Change-Id: I85976e227963c950aad4476d68581b96e1090559
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13373
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Two of the MCT data structures passed as substructures to ramstage were
not packed, and additionally no alignment was specified. On at least
SP5100-based platforms, specifying packed with no alignment caused boot
failure dependent on the exact compiled binary layout (LPC hang).
Specifying the alignment and packing the remaining structures appears to
have resolved the remaining LPC hang issues on the KGPE-D16. Note that
packing the remaining structures alone was not sufficient to eliminate
the hang, however removing the packed attribute entirely (during debugging)
did resolve the hang at the expense of potential problems in ramstage.
Change-Id: If3a7509ed438870d4d05caaaaa091e1c47bf9b97
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14303
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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Change-Id: Iee30a6efb8dcdd04affd5d1105a254781287e9e4
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14253
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This enables CACHE_MRC_SETTINGS by default as well selects
timer configuration.
Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14252
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The SPI controller needs to be set up on devices such as the SP5100
before it can be accessed to write MCT backup data. Move the backup
data write after PCI configuration has been completed.
Change-Id: Ibcf31755242ac058407a422ce8aa33d6b0b293c7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14305
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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ACPI MCFG table is required for OS to support Enhanced
Configuration Space Access.Apollolake will only support
1 PCI Segment Group, so all the pci bus number from 0
to 0xff will belong to that group.
Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13375
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Implement flash read, write, and erase functionality using the
hardware sequencing capabilities of the SOC. Due to changes in
hardware requirements, the flash chip must be probed differently
than on previous platforms (details explained in comments).
Note that this is a minimal implementation, and does not provide all
the bells and whistles.
Change-Id: I6dcc3bc36dfce61927d126d231a16d485acb1bdc
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The delay_tsc.c compilation unit used the C preprocessor
to conditionally compile different code paths. Instead of
guarding large blocks of code allow the compiler to optimize
out unreachable code.
Change-Id: I660c21d6f4099b0d7aefa84b14f1e68d6fd732c3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14302
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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The delay_tsc.c code took different paths depending
__PRE_RAM__ being defined or not. Also, timer_monotonic_get()
was only compiled in a !__PRE_RAM__ environment. Clean up
the code paths by employing CAR_GLOBAL for the global state
which allows the same code to be used in all stages.
Lastly, handle apollolake fallout now that init_timer() is
not needed in placeholders.c.
Change-Id: Ia769fa71e2c9d8b11201a3896d117097f2cb7c56
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14301
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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The current code in delay_tsc.c uses globals and is heavily
guarded by a lot of preprocessor macros. In order to remove
__PRE_RAM__ constraints one needs to use CAR_GLOBAL for the
global variables. Therefore, abstract away direct access to
the globals such that CAR_GLOBAL can be easily employed.
Change-Id: I3350d1a762120476926c8d9f5f5a7aba138daf5f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14300
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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It's not selected by any path so it's a dead option with
associated dead code. Remove the config option as well as
the code paths that were never used any longer.
Change-Id: Ie536eee54e5c63bd90192f413c69e0dd2fea9171
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14299
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
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The LEDs on the beaglebone are connected to GPIOs called USR0-USR3. This
change adds some functions to make it easy to set their value and clear
what the calling code is trying to do.
Change-Id: I0bb83bbc2e195ce1a0104afcd120089efaa22916
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: https://review.coreboot.org/3943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add code for manipulating the GPIOs on the am335x. The API is patterned after
the one used for the Exynos SOCs.
Change-Id: I275317304bd0682f348f72f1c77ed5613065af3f
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: https://review.coreboot.org/3942
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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To avoid having to read/write raw addresses with magic constants,
this change adds data structures which represent the clock module
registers and some constants for how the clock module is used
currently.
Change-Id: I955dae39bbdabccf048a086e706a48c58f620ad4
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: https://review.coreboot.org/3941
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Always use MRC cache if possible.
Added a CRC16 array to make sure the DIMMs haven't been replaced.
In case one of the CRC's doesn't match, start normal RAM training.
Use new fallback in case of broken mrc cache.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Test result:
The system boots a lot faster using the MRC cache.
On swapping DIMMs the CRC16 doesn't match and normal ram training
is started.
Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14172
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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On s3 wakeup h8_enable is called which resets the (audio) volume. But the
volume should be the same as before the s3 state. In particular, userland
programs (e.g. pulseaudio) may be out of sync, if the volume can be changed
by hardware buttons also emitting acpi events. Hence, do not reset the
volume on s3 wakeup.
Tested on a Lenovo ThinkPad X220.
Change-Id: I2af08dea1a3f14a40734d67d372e845cc18c5e09
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-on: https://review.coreboot.org/14183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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The removable DIMM SPD data wasn't read.
As a result the system only uses the 2GB onboard memory and
the GNU Linux kernel paniced in acpi_ds_build_internal_package_obj.
Read the SPD and allow native raminit and MRC blob to use the
removable DIMM.
The system is able to use the removable dimm and the kernel panic
is gone.
Change-Id: I30eed747f924cb0029de55d2ab85c5a94075dc1b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/14278
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This used to build, but will not with newer toolchains.
Change-Id: I0f397839eb85977ba18328b0e32040b15a6c3b0f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/14296
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This resolves error messages of the form:
ERROR: device PNP: 002e.6 index 98 has no mask.
Change-Id: I6a368b902d051c8da6f74cbde54f5d12a3e52c2f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14272
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The default nvm_mmio_to_flash_offset() implementation used by NVM code
in intel/common does not work on apollolake. As a result, provide the
correct override.
Change-Id: I01a94f90dfdd33586a4aac5c05dd8c73e8804437
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14248
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On apollolake, the flash is memory-mapped differently, and the default
MMIO to flash calculation does not produce correct results. While the
long-term solution is to rewrite the NVM functionality to keep the
flash offset as part of its context, as a temporary measure, allow
overriding the to_flash_offset() function by declaring it weak.
Change-Id: Ic54baeba2441a08cfe1a47e235747797f6efb59b
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14247
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit f961becc433bf23fc8744fdfd757f0cdb75c2c62.
On studying the BKDG more closely this is not the correct place
to enable DIMM parity. Further patches to clarify the parity
setup process on Family 15h are forthcoming.
Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebecd
Reviewed-on: https://review.coreboot.org/14271
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
and related changes have made it possible to move the sync flood enable statements
back into romstage.
Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14270
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I55e68c1dba2b5f1d086179af9b3bc30c5e471f6c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14266
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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When a fatal error and subsequent sync flood / reset occurs,
the MCA status registers may contain valuable information on
the cause of the fatal error. Add functions to report MCEs and
reset the MCA status registers early in the boot process.
Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14265
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I42d901ae9445943a863fb3ba9bda5a915f255e02
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14264
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The SB700 family has the ability to report the last reset
reason. This is useful in the context of handling MCEs
and recovering from fatal errors / sync floods.
Add a function to retrieve the last reset flags.
Change-Id: I754cb25e47bd9c1e4a29ecb6cb18017d1b7c3dc4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14263
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Certain AMD platforms, such as those using the SP5100 southbridge,
contain a very poorly documented bug related to LPC ROM access,
which is triggered by repeated (hundreds or more) rapid calls to
get_option(). This bug manifests as a complete system deadlock
in ramstage device configuration, requiring standby power to be
removed from the system to release the deadlock.
Cache the platform ECC status to avoid repeated calls to get_option()
in the lane count detection logic.
Change-Id: I8b48c523218ccc8c113319957d6eca2d15e1070f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14273
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I08d3ba8b64459b1f84a5f1318e37c31010d7ae0f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14251
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This adds boot mode constants. They match EDK2 found in PiBootMode.h
constants but are part of FSP2.0 spec.
Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Include SOC specific FADT tables to current mainboard.
Change-Id: Id4099528657304e9f7675c839e7666c58f189004
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13353
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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Upcoming designs are based on similar SOCs, this patch moves code
which can be reused into a common directory under soc/rockchip.
Changing spi.h to include stdder.h, as this is were check_member() is
defined, this becomes necessary later when the new SOC code is added.
Renaming UART driver private functions not to be bound to any
particular SOC.
BUG=none
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied).
Change-Id: I39a505aecda8849daa58a8eca0e44a5243664423
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f63f2582042ac115481207ddf329ea2e3260e55e
Original-Change-Id: I3a1139305354d460492b25a45f3da315a9a0b49e
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/335408
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14235
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Our EDID code had always been aligning the framebuffer's
bytes_per_line (and x_resolution dependent on that) to 64. It turns out
that this is a controller-dependent parameter that seems to only really
be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper
function to calculate bits-per-pixel dependent values) probably actually
broke this for some other controllers by applying the alignment too
widely.
This patch makes it explicitly configurable and depends the default on
ARCH_X86 (which seems to be the simplest and least intrusive way to make
it fit most cases for now... boards where this doesn't apply can still
override it manually by calling edid_set_framebuffer_bits_per_pixel()
again).
Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14267
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The logic to enable reset on sync flood per RPR guidelines
somehow ended up guarded on the SATA AHCI setup. Unconditionally
enable reset on sync flood per the RPR.
Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14260
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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power_on_after_fail=Enable in cmos.default leads to wake on AC behaviour
on mobile systems. Therefore set cmos.default entry to "Disable" in order
to improve user experience.
Change-Id: I977a4e6bc028c8c4c7fc1c2f5fdd74a59e951c60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/13884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Fill the ACPI FADT table base on apollolake SOC definition.
Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13352
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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In error case die in top level function.
No functionality is changed.
Change-Id: Ie15b01184d40bdbce20d49dcab2f9fb607068c7a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14171
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Return errors to top level ram init function.
Required by the folowing series to implement a fallback.
No functionality is changed.
On error case the system still halts in every test.
Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I76a1047742369416b90e5c8bf307f85c02ae9bbb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14242
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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SP5100 devices are affected by an erratum that can lock up the
EHCI ports under certain conditions. Add an optional CMOS
option to enable a workaround at the expense of performance.
Change-Id: I305d23dfa50f10a3dcb5c731e8923305c8956dde
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14241
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change the existing chromeos.fmd files and the dts-to-fmd script to mark
RW_LEGACY as CBFS, so it's properly "formatted".
BUG=chromium:595715
BRANCH=none
TEST=none
Change-Id: I76de26032ea8da0c7755a76a01e7bea9cfaebe23
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 717a00c459906fa87f61314ea4541c31b50539f4
Original-Change-Id: I4b037b60d10be3da824c6baecabfd244eec2cdac
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/336403
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14240
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The codepath was untested and incomplete. It now determines the right
GBB region sizes and puts the data in.
BUG=chromium:595715
BRANCH=none
TEST=none
Change-Id: I2cc47ddd8aa7675375ca5ed5f75632c30c65dd1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 36e026404ed049d61b677ef043a781c8c209dd93
Original-Change-Id: Ib872627740dbd8ac19fc3e2a01464457f38366ed
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/336358
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14239
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This mirrors vboot's flag table.
BUG=chromium:595715
BRANCH=none
TEST=none
Change-Id: I4473eb6c0e073f555e6a692a447e8cc85f8e4eeb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0fc50a6cff5ba900e6407d58a8f18db63b5946a5
Original-Change-Id: Ieabd3f9391ba256557e18386f334558d64a81694
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/336630
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14238
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=none
BRANCH=none
TEST=emerge-oak coreboot
Change-Id: Ia5f2bc9b021b9051f2e5035c5d295b6b9eea1301
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7304016041d42a5317448fc2f9c58c6e6715fc25
Original-Change-Id: I7bcd1cf8dabbe190fcbc62cbf6b3a34430a97b21
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/336592
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14236
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The MT8173 hardware watchdog can assert an external signal which we use
to reset the TPM on Oak. Therefore we do not need to do the same
double-reset dance as on other Chromebooks to ensure that we reset in a
correct state.
Still, we have a situation where we need to reconfigure the watchdog
early in the bootblock in a way that will clear information about the
previous reboot from the status register, and we need that information
later in ramstage to log the right event. Let's reuse the same watchdog
tombstone mechanism from other boards, except that we don't perform a
second reset and the tombstone is simply used to communicate between
bootblock and ramstage within the same boot.
BRANCH=None
BUG=None
TEST=Run 'mem w 0x10007004 0x8' on Oak, observe how it reboots and how
'mosys eventlog list' shows a hardware watchdog reboot event afterwards.
Change-Id: I1ade018eba652af91814fdaec233b9920f2df01f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07af37e11499e86e730f7581862e8f0d67a04218
Original-Change-Id: I0b9c6b83b20d6e1362d650ac2ee49fff45b29767
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/334449
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14234
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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