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2019-12-27src/include: Remove min/max() from <stdlib.h>Elyes HAOUAS
Change-Id: I9ded44422a267e244343502dd5d6ab355e5a788d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37378 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27mb/*/*/early_init.c: Remove defined but not used macroElyes HAOUAS
Change-Id: I69c3b0b96fde8dc44a961c3d687f5aadbbdddde0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37644 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26nb/haswell/minihd: correct subsystem IDMatt DeVillier
The subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: I74cbba31e93f9bb5b18d3ada780a0f24614ba029 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26soc/broadwell/minihd: correct vendor, subsystem IDsMatt DeVillier
Codec vendor ID was copy/pasted from Haswell, should be 0x80862808. Subsystem ID for Intel Mini-HD is always 0x80860101. Change-Id: Idf4446d3437de0dc533baa3b2b4eb49f816807a6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37860 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26mb/google/hatch: Clean up duplicate methodEric Lai
Moving Enable/disable GPIO clock gating to soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26mb/google/octopus/variants/dood: support LTE moduleRen Kuo
related LTE GPIOs: GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:146843935 BRANCH=octopus TEST=build and verify on the DUT with LTE Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Ief6c993ede2bb4b3effbb05cfe22b7af4fcf7faf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26mb/google/octopus/variants/bobba: fix LTE power sequence and moveSheng-Liang Pan
get_board_sku to smm stage. fix Power_off section power sequence. power_off_lte_module() should run in smm stage, add variant.c in smm stage. also move get_board_sku() to mainboard_misc.c so that we can use it in smm stage and ramstage. BUG=b:144327240 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I287ba1cb092a95b3a9dd1f960a3b84fd85b9b221 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37649 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26mb/google/octopus: Add two new sku IDs for foobTommie
Declare these sku IDs: -SKU: 1 Foob, 1-cam, no touch, no pen. -SKU: 9 Foob360, 2-cam, touch, pen. BUG=b:145837644 BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com> Change-Id: Iffcbb3f6f945ea299ff687a383a82b88dcd11ea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26soc/intel/cannonlake: Move GPIO PM configuration to soc levelEric Lai
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits. Restore the PM bits when exit s0ix/Sx. BUG=b:144002424 TEST=Check GPIO PM bits when enter/exit s0ix are expected Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26drivers/generic/cbfs-serial: Add driver to read serial from CBFSMatt DeVillier
Add a new driver to support reading a board serial number from a text file in CBFS and injecting into the SMBIOS tables. Allow driver to be selected at the .config level and not require inclusion at the board level. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26src/x86|cpu/intel: Hardcode FIT and IDMarshall Dawson
Revert two of the changes made in "arch|cpu/x86: Add Kconfig option for x86 reset vector" I6a814f7179ee4251aeeccb2555221616e944e03d The Intel FIT pointer and the ID section should be offsets from the top of flash, and aren't inherently tied to the reset vector or to bootblock. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26soc/amd/picasso: Configure APOB NV only with ACPI resumeMarshall Dawson
The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26mb/google/hatch/akemi: Set touchpad data hold time more thanPeichao Wang
300ns According to SI team and vendor request, need to tune I2C bus 0 data hold time more than 300ns BUG=b:146163044 TEST=build firmware and measure I2C bus 0 data hold time Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37322 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26mb/google/eve: select SYSTEM_TYPE_CONVERTIBLEMatt DeVillier
select SYSTEM_TYPE_CONVERTIBLE, which properly sets the SMBIOS chassis type, and allows the OS driver to recognize tablet mode capability Change-Id: Ic61659e9fa6f7428afd1f018fb8cb25fe49e8747 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26mb/google/kefka: Add missing SPDMatt DeVillier
Adapted from Chromium commit 9522225e [Kefka: Add memory SPD info for Hynix H9CCNNN8GTALAR-NUD] Add current available ram_id to support Hynix H9CCNNN8GTALAR-NUD spd info. RAM_ID: 0110 4GiB Hynix H9CCNNN8GTALAR-NUD RAM_ID: 0111 2GiB Hynix H9CCNNN8GTALAR-NUD Original-Change-Id: I48386ff3e5f80de94ea87359a09a5ec2577043b5 Original-Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/664517 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I0ae76c4d8313246927bbc3f71b21f3611c89a6e3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26mb/google/eve: Update and fix VBTMatt DeVillier
Update Eve's VBT from v211 to v221, and change the backlight control type from PWM to VESA eDP/AUX. This allows the OS to select the proper backlight control type for the panel. Test: Eve backlight control now functional under Windows 10 (Linux requires some pending patches to fix) Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26src: Remove unused include <string.h>Elyes HAOUAS
Change-Id: Ic6b66dd8fa387e67bb0ce609fb7e2553eeb66b3c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-26hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlonWisley Chen
In https://review.coreboot.org/c/coreboot/+/37459 (commit fcd8c9e99e7f70e2b9494f2fa28a08ba13126daa) which moves power/reset pin control of FPMCU to var/board/ramstage, but does not implement it for dratini/jinlon. So, add it in dratini/jinlon. BUG=b:146366921 TEST=emerge-hatch coreboot Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26soc/intel/cannonlake: Clean up report_cpu_info() functionUsha P
This patch makes below clean-up for report_cpu_info() function. 1. Remove unused variables. 3. Reuse fill_processor_name. TEST = Successfully able to boot hatch and verify the cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz" Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26soc/intel/cannonlake: Refactor pch_early_init() codeUsha P
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBus init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot hatch successfully. Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26soc/intel/skylake: Rename pch_init() codeUsha P
This patch renames pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot soraka successfully. Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-26vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger LakeSubrata Banik
Add header files for FSP for Tiger Lake platform version 2457. Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-12-26mb/google/hatch/var/jinlon: Update DPTF parametersWisley Chen
The change applies the DPTF parameters received from the thermal team. BUG=b:146540028 TEST=build and verified by thermal team. Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-26mb/google/octopus/variants/garg: update new SKUKevin Chiu
add new SKU ID below: 19 - Garg PVT (HDMI DB, Touch) 20 - Garg PVT (2A2C DB, Touch) 38 - Garg360 EVT (2A2C DB, touch, no stylues, rear camera) BUG=b:146260545 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Ic74ce14db7060f3124c1a277eb3625ce0ff0b9f0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26mb/gigabyte/ga-b75m-d3h: enable superspeed ports for all variantsBill XIE
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions to wire SuperSpeed-capable ports to XHCI in its devicetree, causing these ports being wired to the second EHCI, and only working as USB 2.0 ports. The missing register definitions are added to fix that. Tested on my ga-b75-d3v board. Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26soc/amd/common/car: Remove unneeded headerKyösti Mälkki
Change-Id: I9c65d3c54efcdec1ebb2648d078acdd9e7c11c49 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-26cpu/intel/car/p4-netburst: Add assert for SIPI_VECTOR_IN_ROMKyösti Mälkki
Location of _start16bit in entry16.inc is about to see some changes, lets make sure they don't break the alignment requirement here. Change-Id: Id8a0964982387e5321e8c89254922e1242cf85ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-26asus/am1i-a: Switch away from ROMCC_BOOTBLOCKMike Banon
Switching was done by moving a SIO configuration and the clocks setup from 'romstage.c' to 'bootblock.c', following the example of change CB:37719 (fc749b2). TEST=Boots into Artix Linux 2019 without a problem. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-25mb/supermicro/x11-lga1151-series: Remove default devicetree valuesPatrick Rudolph
The same default values are used if the values are not present in devicetree. Change-Id: Ic910cdc8077e1b3e98eadc77a2d1fa0f9cb38e5b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner
2019-12-25soc/intel/skylake/vr_config: Use lookup table by defaultPatrick Rudolph
If the board doesn't provide VRconfig in devicetree make sure to use the lookup table for IccMax instead of defaults for some mobile SoC. Also use decimal values instead of hex. Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37598 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25mainboard/google/puff: Add GPIO configurationEdward O'Callaghan
BUG=b:144809606,142094759 BRANCH=none TEST=none Change-Id: Iae20d2262c910044dde84f10d795f4aee3318532 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Signed-off-by: Kangheui Won <khwon@chromium.org> Co-Author: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37925 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25mb/google/hatch/variant/kohaku: Fix Kohaku baseboard/gpio.c mux commentsEdward O'Callaghan
Follow MEM_STRAP_* comment style to be consistent with other boards. BUG=b:144809606 BRANCH=hatch TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4945f676f307af9b8c0baa1fbcaf33113de647c3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-25mainboard/google/hatch: Move gpio GPP_H3 config up from baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_H3 gpio config for easier review. This toggles the MAX amp which not all boards have. Move the pin configuration to boards with the respective devicetree configuration following on from the theme of commit b417786525. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mainboard/google/hatch: Move gpio GPP_C* NC down into baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_C15 group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-25mainboard/google/hatch: Move gpio GPP_A* NC down into baseboardEdward O'Callaghan
The baseboard GPIO table definitions are too straineous to the extend that variants need to redefine assumptions back to NC. Invert this so that baseboard by default assumes the safer NC and move the specific board configurations to their respective places. This patch handles the GPP_A* group for easier review. BUG=b:142094759 BRANCH=none TEST=builds Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-24mainboard/variant/puff: set PL values for puffKangheui Won
To be safe for now, don't differentiate between SKUs and use lower values to ensure board won't be browned out. BUG=b:143246320 TEST=none BRANCH=none Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9 Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37651 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-24vendorcode/amd/pi/Kconfig: Add prompt to pre/post pi filesRaul E Rangel
This allows the values to be set in a .config BUG=none TEST=Was able to set the value from a .config and built careena firmware Change-Id: I757e4b9a0b80ff42c1f49143a44f15550366fd0b Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37879 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-24mainboard/google/hatch: Remove MAX98357A assumption from baseboardEdward O'Callaghan
Generally work towards a more loose baseboard definition by moving out some original assumptions to be board specifics. Specifically Puff does not have the MAX98357A speaker amp and enabling the driver winds up generating incorrect SSDT tables that confuse the kernel. Since devicetree inherits the chip from device node in base and an override will also inherit the chip and thus dispatch the unwanted fill_ssdt fn call. V.2: lean on linker to drop max98357a driver when not in dt. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37909 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-23mainboard/google/puff: Configure HDA registersEdward O'Callaghan
Enable PCH HDA and configure dmic+ssp registers. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If9495261201ca256cdb35352338c0b3a82a50196 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-12-23mainboard/google/puff: Enable func0 of 1c for nicEdward O'Callaghan
Two things here: i. ) FSP requires that function 0 be enabled whenever any non-zero functions hang under the same bus:device. ii.) FSP reorders function 6 RP to be function 0 if function 0 is indeed unused. BUG=b:146437819 BRANCH=none TEST=none Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-22superio/common: Add more ACPI methodsPatrick Rudolph
* Make use of introduced SSDT config mode access * Make use of introduced SSDT mutex * Provide ACPI functions to safely access SIO config space * Implement method to query LDN enable state * Implement method to set LDN enable state * Use introduced functions to implement _DIS and _STA in the device * Update documentation Tested on Aspeed AST2500 and Linux 5.2. Manually verified ACPI code that generates no errors in Linux. Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-22superio/common/conf_mode: Add op to write SSDTPatrick Rudolph
Add functions to write ACPI SSDT code for entering and leaving the config mode. To be used by ACPI generators. Tested on Linux 5.2 using the Aspeed SSDT generator. Change-Id: I14b55b885f1c384536bafafed39ad399639868e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-21mb/**/dsdt.asl: Remove "Some generic macros" commentAngel Pons
It provides no useful information, so it might as well vanish. Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-21sb/amd/{agesa,pi,cimx}/bootblock: Use simple PCI config accessorKyösti Mälkki
Change-Id: I5e1f2ceda37927d7a75660affee8504f9f8aff15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37597 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-21sb/amd/{agesa,pi}/hudson: Use simple PCI config accessorKyösti Mälkki
Change-Id: I3d8e21e17a0f870d854694e326b10f7d2d04e5ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37596 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCKKyösti Mälkki
Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20src/mainboard: Remove unused '#include <device/pci.h>'Elyes HAOUAS
Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-20mainboard: Add missing include <device/pci_def.h>Elyes HAOUAS
Change-Id: I8a7c989540e8b62de7fd291f695adac849f4680c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-20security/vboot: Add a dedicated flag for building of vboot libraryBill XIE
As discussed in CB:35077, since both measured boot and verified boot depends on vboot library, it had better to introduce a dedicated flag CONFIG_VBOOT_LIB to control the building and linking of the vboot library, and make other flags needing vboot library select it. Only the actual verification stuff should be conditional on CONFIG_VBOOT. Change-Id: Ia1907a11c851ee45a70582e02bdbe08fb18cc6a4 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-12-20soc/intel/tigerlake: Update FSP stack and heap sizeMaulik V Vaghela
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 09:56:46 +0000