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2017-01-25mb/intel/d510mo: Add cmos.layout and cmos.defaultArthur Heymans
Change-Id: I877d4470b697d6a6d4652ed1c60028cdcbe8df98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-25nb/intel/pineview: Make preallocated igd memory a cmos parameterArthur Heymans
Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18142 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-25google/pyro: Modify Wacom touchscreen IRQ type to level-triggeredKevin Chiu
Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-24arch/x86: do not define type of SPIN_LOCK_UNLOCKEDPatrick Georgi
This fixes building coreboot with -std=gnu11 on gcc 4.9.x Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing type. Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18220 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-24Revert "chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections"Patrick Georgi
This reverts commit 580db7fd9036134b1da4fe7340e306fee4681659. There's a (parallel) mechanism more closely aligned with how the values are filled in (fixed device part + version string) that landed from Chrome OS downstream (see commit 4399b85fdd). Change-Id: I5ccd06eadabb396452cc9d1d4dff780ea0720523 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18205 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24google/eve: Enable PD MCU deviceDuncan Laurie
In order for PD charge events to properly notify the OS when a charger is attached we need to enable the PD MCU device and event source from the EC. Without this change the charging still happens, but the OS does not notice and update the charge state icon in the Chrome OS UI. BUG=chrome-os-partner:62206 BRANCH=none TEST=plug in a charger to either port and see charge status updated to indicate charging in the power_supply_info tool and the Chrome OS UI. Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18209 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-24mainboard/lenovo: Add new port L520Patrick Rudolph
Add support for Lenovo Thinkpad L520. The files are generated by autoport, and are successfully tested on the board. L520 has got 4MiB flash chip, that contains a "slim" ME with 1.2MiB only. The flash IC has to be desoldered, as it won't be accessible in circuit. It is located on top of the mainboard right under the touchpad. Test-setup: Extract the following blobs from vendor BIOS: * Intel Flash Descriptor * Intel Management Engine * Intel VBios The laptop has been externaly flashed. It was able to turn on the display and load SeaBIOS. Latest debian has been booted from harddisk. Latest fedora has been booted from USB flash drive. The following hardware has been tested and is working: * Display using Option Rom * PCIe wifi * Ethernet * Keyboard, trackpoint and touchpad * Some Fn functions keys * Volume Keys (except mic mute) * Status LEDs * Audio (headphone jack only) * USB ports * Native raminit dual channel (2 DDR3-1333 DIMMs tested) * SATA cdrom * SATA harddrive Broken: * Some Fn functions keys * Microphone mute button * Speakers (but headphone jack gives sound) Untested: * Expansion slot * SD card slot * Docking station * Native gfx init The EHCI debug port is the first one on the right side. Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18003 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-24mainboard/intel/leafhill: initial leafhill board changesBrenton Dong
This commit makes the initial changes to support the Intel Leaf Hill CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set. The google/reef directory is used as a template, and the same IFWI stitching process as reef is used to generate a bootable image. Apollo Lake silicon requires a boot media region called IFWI which includes assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware. Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18039 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-24drivers/intel/gma/vbt: Fix style and minor issuesNico Huber
o Fix indentation and other whitespace issues, o Use `const` where applicable, o Avoid retyping the same constant literals, o Actually read PCI revision from the device (instead of using the lowest class byte). Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18185 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-24mainboard/intel: add leafhill board directoryBrenton Dong
This commit adds the initial scaffolding for the Intel Leafhill CRB with Apollo Lake silicon. The google/reef directory is used as a template. This commit only makes the minimum changes to Kconfig and Kconfig.name needed for the build bot to not have issues. Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18038 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-24vboot: vb2ex_printf() ignores null function nameRandall Spangler
Currently, it will print the function name as a prefix to the debug output. Make it so that a null function name won't get printed, so that it's possible to print little bits of debug output. BUG=chromium:683391 BRANCH=none TEST=build_packages --board=reef chromeos-firmware Change-Id: I046fa766773fc08a29460db1f884d7902692d182 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 853ff7176e97e5e1ab664d094e1914c9c94510aa Original-Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9 Original-Signed-off-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/431111 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18204 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24rockchip/rk3399: set edp pclk to 25MHzLin Huang
It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1 passive trigger points. CPU passive point: 80 TSR1 passive point: 46 2. Update DPTF TRT Sample Period TSR1: 8s BUG=chrome-os-partner:62133 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: I54ef3e8dd79670bdb037baeec91430113d11bcc1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c58788026f28af52c650da0159b93d97269ca4a9 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/18176 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-22nb/x4x/raminit: Fix programming dram timingsArthur Heymans
The results were obtained by comparing the MCHBAR registers of vendor bios with coreboot at the same dram timings. This fixes 2 issues: * 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with 800MHz raminit failed; * 1067MHz fsb CPUs did not boot when second dimm slot was populated. TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with DDR2 667 and 800MHz dimms. Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18022 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-22mainboard/google/reef: Increase TSR1 trigger pointTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.4_20170120.xlsx) 1. Update DPTF TSR1 passive trigger point. TSR1 passive point: 46 BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: If35e4cf2dbf7c506534c52a052598f6204d5315a Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Fixes for devicetree settingsDuncan Laurie
The devicetree settings were incorrect in a few places with respect to the SOC and board design: - IMVP8 VR workaround is for MP2939 and not MP2949 on Eve - IccMax values are incorrect according to KBL-Y EDS - USB2[6] is incorrectly labeled - I2C touch devices do not need probed as they are not optional - PCIe Root Port 5 should be enabled - I2C5 device should not be enabled as it is unused BUG=chrome-os-partner:58666 TEST=manually tested on Eve board Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18200 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Enable separate recovery MRC cacheDuncan Laurie
In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22soc/intel/skylake: Include I2C code in romstageDuncan Laurie
The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Enable keyboard backlight in bootblockDuncan Laurie
Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18197 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21soc/intel/apollolake: correct GPIO 13 IRQ numberAaron Durbin
The define for GPIO_13_IRQ had the wrong IRQ number. It should be 0x70 instead of 0x6f. BUG=chrome-os-partner:62085 BRANCH=reef TEST=touch controller doesn't indicate continuous interrupts Change-Id: I3a0726db59fc1eb7736d348aecbf1082719f15b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21mainboard/google/reef: remove internal pullups on PP1800_S railAaron Durbin
The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18189 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21pcengines/apu2: Add serial number in SMBIOSKyösti Mälkki
Change-Id: Ic8149b1dd19d70935e00881cffa7ead0960d1c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18154 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2017-01-21pcengines/apu2: Add SKU in SMBIOSKyösti Mälkki
Installed memory only, PCB revision cannot be detected. Change-Id: Ib6224018db3de4a7ddd9e6f7f30edc438c3f0702 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18153 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Refactor reading memory strapKyösti Mälkki
Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Change SMBIOS part numberKyösti Mälkki
This string should not include manufacturer name. Change-Id: I63793b16129334ea4930b8b0264a39d7f9849bba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18151 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Remove DDI configurationKyösti Mälkki
Assembled SoC part does not have integrated graphics. Change-Id: I5d157063cd850d343df73d448e6904c188a09730 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18150 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-20nb/gm45/gma.c: Fix reported Pixel clockArthur Heymans
Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18180 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-20lb_tables: make lb_mainboard and lb_strings record sizes 64-bit alignedRonald G. Minnich
They were sized to 32-bit alignment, this grows them to 64 bit-aligned. Change-Id: I494b942c4866a7912fb48a53f9524db20ac53a8c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/18165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-20google/snappy: Add weida touchscreen supportWisley Chen
Add weida touchscreen as 2nd touchscreen source BUG=chrome-os-partner:61865 BRANCH=reef TEST=emerge-snappy coreboot, and verified that touchscreen works on snappy. Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20google/snappy: Use exported GPIOs and ACPI regulator for touchscreenWisley Chen
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=None BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1Barnali Sarkar
As per Audio PCH team recommendation the iDisplay Audio/SDIN2 should be disabled to bypass InitializeDisplayAudio() function call. Display Audio Codec is HDA-Link Codec, which is not supported in I2S mode BUG=chrome-os-partner:61548 BRANCH=none TEST=Tested to verify that InitializeDisplayAudio() does not get called. Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18091 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-20google/eve: Adjust DPTF parametersDuncan Laurie
- Remove the 0mA entry for the charger performance table - Slightly raise the passive limit for TSR2/TSR3 to 55C BUG=chrome-os-partner:58666 TEST=manual testing on P1 system Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18172 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20google/eve: Enable ACPI keyboard backlightDuncan Laurie
Enable the ACPI interface to EC driven keyboard backlight. BUG=chrome-os-partner:61464 TEST=manual testing on P1 system Change-Id: I13d96c13d7db726b1e8289131db65104bd302efe Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18171 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20google/eve: Enable pull-up on ACPRESENTDuncan Laurie
Enable an internal pull-up on ACPRESENT signal. BUG=chrome-os-partner:58666 TEST=manual testing on P1 Change-Id: I0bb86f4547272e021ffd10998faa0e2f103b0808 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18170 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-19mainboard/google/snappy: Disable unused devicesWisley Chen
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-19mainboard/google/reef: Ignore Audio DMIC IOSSTATEVaibhav Shankar
Audio DMIC PLL needs to be ON in S0ix to support Wake on Voice. This requires GPIO_79 and GPIO_80 to be configured as IGNORE IOSSTATE. So DMIC CLKs will be ON in S0ix. Change-Id: If91045a8664ce853366b670b9db38d620818fbab Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-19driver/intel/fsp1_1: Fix boot failure for non-verstage caseTeo Boon Tiong
Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19soc/intel/skylake: Add SATA interrupt for APIC modeSooi, Li Cheng
Add SATA interrupt for APIC mode Change-Id: I9e0682e235715399da2c585174925c89b9116ab3 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18130 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19nb/amd/ddr3: Make the maximum CDD a signed valueTimothy Pearson
max_cdd_we_delta should be signed to allow for negative CDD. Found-by: Coverity Scan #1347355 Change-Id: Iaccd1021680296d169c26c25e339f83fbd7cc065 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-17Revert "mainboard/google/snappy: Add PowerResource for ELAN touchscreen"Martin Roth
This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource for ELAN touchscreen) Change was out of date and broke the build. Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-17mainboard/google/reef: Ignore SPI IOSTANDBYLijian Zhao
SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/18137 Tested-by: build bot (Jenkins) Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17mainboard/google/snappy: Add PowerResource for ELAN touchscreenWisley Chen
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17366 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17Combine Baytrail ChromeOS devices using variant schemeMatt DeVillier
Combine existing boards google/enguarde and google/ninja using their common reference board google/rambi as a baseboard. Variants contain board specific data: - DPTF ACPI components - I2C ACPI devices - RAM config / SPD data - devicetree config - GPIOs - board-specific HW components (e.g., LAN) Additionally, some minor cleanup/changes were made: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) The existing enguarde and ninja boards are removed. Variant setup modeled after google/auron Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17google/enguarde,ninja: Prep for variant mergeMatt DeVillier
Minor cleanup for enguarde and ninja devices: - enguarde: correct trackpad I2C slave address - enguarde: remove unused trackpad ACPI devices - ninja: remove unused PS2 keyboard ACPI device Change-Id: I1beb34059ba318e2d496a59e4b482f3462faf232 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-16intel: Fix copy/paste error in license textMarshall Dawson
Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-16riscv: Move mcall numbers to mcall.h, adjust their namesJonathan Neuschäfer
The new name and location make more sense: - The instruction used to call into machine mode isn't called "ecall" anymore; it's mcall now. - Having SBI_ in the name is slightly wrong, too: these numbers are not part of the Supervisor Binary Interface, they are just used to forward SBI calls (they could be renumbered arbitrarily without breaking an OS that's run under coreboot). Also remove mcall_dev_{req,resp} and the corresponding mcall numbers, which are no longer used. Change-Id: I76a8cb04e4ace51964b1cb4f67d49cfee9850da7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18146 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16riscv/spike: Remove obsolete DRAM_SIZE_MB settingJonathan Neuschäfer
Change-Id: I4077739ac2be09107d8c5a3e4ae7ebd0da3cb876 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16mainboard/google/poppy: SD card changesFurquan Shaikh
1. Disable WP 2. Pass SD card detect info in ACPI BUG=chrome-os-partner:60713 BRANCH=None TEST=Verified that OS is able to detect SD card and read/write to it. Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-16mainboard/google/poppy: Update DQS and DQ Byte mappings for poppyRizwan Qureshi
poppy schematics have undergone change after review, update DQS and DQ Byte mappings based on the new schematics. BUG=chrome-os-partner:61856 BRANCH=None TEST= Build and boot all the poppy proto SKUs to OS. Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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