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2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
New microcode released this week. Change-Id: I426d0e00d1c03650049cbe033b53a909a7d944c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 63ec6438b566d14a2b878474ca068cf70d9aa9d6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6966 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
This broadwell implementation will support Haswell ULT in addition to broadwell CPUs. Add the latest available microcode for the broadwell C0 and D0 parts as well as Haswell ULT. Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198742 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 69d5b7c834a4f52656ab14562ea913477418e588) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6965 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: add new intel SOCDuncan Laurie
broadwell: Import files from haswell/lynxpoint into soc/broadwell Reviewed-on: https://chromium-review.googlesource.com/198425 (cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af) broadwell: Unify and clean up license Reviewed-on: https://chromium-review.googlesource.com/198426 (cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d) broadwell: pch.h: split PM into new header Reviewed-on: https://chromium-review.googlesource.com/198427 (cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373) broadwell: pch.h: split RCBA into new header Reviewed-on: https://chromium-review.googlesource.com/198428 (cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135) broadwell: pch.h: split SATA into new header Reviewed-on: https://chromium-review.googlesource.com/198429 (cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71) broadwell: pch.h: split SPI into new header Reviewed-on: https://chromium-review.googlesource.com/198550 (cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14) broadwell: pch.h: split SerialIO into new header Reviewed-on: https://chromium-review.googlesource.com/198551 (cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6) broadwell: pch.h: split LPC into new header Reviewed-on: https://chromium-review.googlesource.com/198552 (cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102) broadwell: pch.h: split GPIO into new header and clean up Reviewed-on: https://chromium-review.googlesource.com/198553 (cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5) broadwell: pch.h: split USB into new headers Reviewed-on: https://chromium-review.googlesource.com/198554 (cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068) broadwell: Split IOBP into separate files Reviewed-on: https://chromium-review.googlesource.com/198734 (cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600) broadwell: smbus: Extract common code and split header Reviewed-on: https://chromium-review.googlesource.com/198735 (cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d) broadwell: Create iomap.h header with platform base addresses Reviewed-on: https://chromium-review.googlesource.com/198736 (cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee) broadwell: Add header for platform PCI devices Reviewed-on: https://chromium-review.googlesource.com/198737 (cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500) broadwell: Split SMM related defines/prototypes to new header Reviewed-on: https://chromium-review.googlesource.com/198738 (cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4) broadwell: cpu.h: Split MSR defines to separate header Reviewed-on: https://chromium-review.googlesource.com/198739 (cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805) broadwell: Create romstage header file Reviewed-on: https://chromium-review.googlesource.com/198740 (cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21) broadwell: Create ram stage header file Reviewed-on: https://chromium-review.googlesource.com/198741 (cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621) broadwell: Add reference code data interface Reviewed-on: https://chromium-review.googlesource.com/198743 (cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95) broadwell: Clean up ACPI NVS region Reviewed-on: https://chromium-review.googlesource.com/198897 (cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14) broadwell: Move CTDP ACPI methods to new file Reviewed-on: https://chromium-review.googlesource.com/198898 (cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2) broadwell: Split EHCI and XHCI ACPI devices Reviewed-on: https://chromium-review.googlesource.com/198899 (cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca) broadwell: ACPI: Clean up SerialIO ACPI code Reviewed-on: https://chromium-review.googlesource.com/198910 (cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35) broadwell: ACPI: Remove special handling of LPT-LP chipset Reviewed-on: https://chromium-review.googlesource.com/198911 (cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6) broadwell: ACPI: Clean up use of base address defines Reviewed-on: https://chromium-review.googlesource.com/198912 (cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75) broadwell: ACPI: Clean up and fix formatting Reviewed-on: https://chromium-review.googlesource.com/198913 (cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050) broadwell: Add header for ACPI defines and prototypes Reviewed-on: https://chromium-review.googlesource.com/198914 (cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9) broadwell: Add reset_system function and header Reviewed-on: https://chromium-review.googlesource.com/198915 (cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef) broadwell: Move PCODE MMIO defines to systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198916 (cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f) broadwell: Unify chip.h and add chip.c Reviewed-on: https://chromium-review.googlesource.com/198917 (cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1) broadwell: Rename HASWELL_BCLK to CPU_BCLK Reviewed-on: https://chromium-review.googlesource.com/198918 (cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1) broadwell: Clean up broadwell/cpu.h Reviewed-on: https://chromium-review.googlesource.com/198919 (cherry picked from commit 17353803babc8ace279e105c012130678226144e) broadwell: Clean up broadwell/systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198920 (cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae) broadwell: Clean up broadwell/pch.h Reviewed-on: https://chromium-review.googlesource.com/198921 (cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b) broadwell: Clean up management engine driver Reviewed-on: https://chromium-review.googlesource.com/198922 (cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72) broadwell: Add common CPUID and PCI Device ID defines Reviewed-on: https://chromium-review.googlesource.com/198923 (cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8) broadwell: Clean up and expand report_platform Reviewed-on: https://chromium-review.googlesource.com/198924 (cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022) broadwell: Clean up the bootblock code Reviewed-on: https://chromium-review.googlesource.com/198925 (cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c) broadwell: Clean up ramstage device and driver operations Reviewed-on: https://chromium-review.googlesource.com/199180 (cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569) broadwell: Clean up XHCI and EHCI ramstage drivers Reviewed-on: https://chromium-review.googlesource.com/199181 (cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d) broadwell: Clean up gpio handling code Reviewed-on: https://chromium-review.googlesource.com/199182 (cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20) broadwell: Clean up the PCH generic code Reviewed-on: https://chromium-review.googlesource.com/199183 (cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff) broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c Reviewed-on: https://chromium-review.googlesource.com/199184 (cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7) broadwell: Clean up pmutil.c Reviewed-on: https://chromium-review.googlesource.com/199185 (cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84) broadwell: pmutil: Add new acpi_sci_irq() function Reviewed-on: https://chromium-review.googlesource.com/199186 (cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5) broadwell: Clean up HDA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199187 (cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d) broadwell: Clean up cache_as_ram assembly Reviewed-on: https://chromium-review.googlesource.com/199188 (cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d) broadwell: romstage: Separate stack helper functions Reviewed-on: https://chromium-review.googlesource.com/199189 (cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad) broadwell: Add function to read WPSR from SPI Reviewed-on: https://chromium-review.googlesource.com/199190 (cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a) broadwell: Clean up SMBUS code in romstage and ramstage Reviewed-on: https://chromium-review.googlesource.com/199191 (cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa) broadwell: SPI: Clean up romstage and ramstage code Reviewed-on: https://chromium-review.googlesource.com/199192 (cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf) broadwell: Clean up PCIe root port ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199193 (cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e) broadwell: Clean up minihd ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199194 (cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e) broadwell: Update romstage main to follow baytrail format Reviewed-on: https://chromium-review.googlesource.com/199361 (cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd) broadwell: Add CPU set_max_freq function for romstage Reviewed-on: https://chromium-review.googlesource.com/199362 (cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6) broadwell: romstage: Add chipset_power_state implementation Reviewed-on: https://chromium-review.googlesource.com/199363 (cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c) broadwell: romstage: Convert systemagent init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199364 (cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2) broadwell: romstage: Convert pch init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199365 (cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c) broadwell: elog: Use chipset_power_state for events Reviewed-on: https://chromium-review.googlesource.com/199366 (cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9) broadwell: Clean up SATA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199367 (cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8) broadwell: Update ramstage graphics driver to support broadwell Reviewed-on: https://chromium-review.googlesource.com/199368 (cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281) broadwell: Update raminit to follow baytrail layout Reviewed-on: https://chromium-review.googlesource.com/199369 (cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523) broadwell: Update and unify the finalize steps Reviewed-on: https://chromium-review.googlesource.com/199390 (cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa) broadwell: Clean up SMM code Reviewed-on: https://chromium-review.googlesource.com/199391 (cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd) broadwell: Clean up LPC ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199392 (cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e) broadwell: Clean up systemagent ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199393 (cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3) broadwell: Move C-state configuration information to acpi.c Reviewed-on: https://chromium-review.googlesource.com/199394 (cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990) broadwell: Clean up CPU ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199395 (cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969) broadwell: Do not reserve SMM relocation region Reviewed-on: https://chromium-review.googlesource.com/199402 (cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c) broadwell: Add an early ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199403 (cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3) broadwell: Support for second reference code binary Reviewed-on: https://chromium-review.googlesource.com/199404 (cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2) broadwell: Clean up serialio init code Reviewed-on: https://chromium-review.googlesource.com/199405 (cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489) broadwell: acpi: Add function to fill out FADT Reviewed-on: https://chromium-review.googlesource.com/199406 (cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74) broadwell: Update C-state table creation Reviewed-on: https://chromium-review.googlesource.com/199407 (cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063) broadwell: acpi: Clean up acpi table creation code Reviewed-on: https://chromium-review.googlesource.com/199408 (cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146) broadwell: acpi: Add ACPI table create helper functions Reviewed-on: https://chromium-review.googlesource.com/199409 (cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c) broadwell: Add soc/intel/broadwell Makefiles Reviewed-on: https://chromium-review.googlesource.com/199410 (cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc) broadwell: Add Kconfig for broadwell soc Reviewed-on: https://chromium-review.googlesource.com/199411 (cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe) Squashed 78 commits for broadwell that form a solid code base. Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6964 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
This is common code for Intel SOC that can be shared. Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3a9057b9616c54a8404eee55511743d2492dbc28) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
baytrail: Change all GPIO related pull resistors from 10K to 20K Reviewed-on: https://chromium-review.googlesource.com/187570 (cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e) baytrail: workaround kernel using serial console on resume Reviewed-on: https://chromium-review.googlesource.com/188011 (cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469) baytrail: allow dirty cache line evictions for SMRAM to stick Reviewed-on: https://chromium-review.googlesource.com/188015 (cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca) baytrail: Optionally pull up TDO and TMS to avoid power loss in S3. Reviewed-on: https://chromium-review.googlesource.com/188260 (cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6) rambi: always load option rom Reviewed-on: https://chromium-review.googlesource.com/188721 (cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9) baytrail: use new chromeos ram oops API Reviewed-on: https://chromium-review.googlesource.com/186394 (cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594) rambi: always show dev/rec screens on eDP connected panel Reviewed-on: https://chromium-review.googlesource.com/188731 (cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95) baytrail: stop e820 reserving default SMM region Reviewed-on: https://chromium-review.googlesource.com/189084 (cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24) baytrai: update MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/189196 (cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970) rambi: Put LPE device into ACPI mode Reviewed-on: https://chromium-review.googlesource.com/189371 (cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413) baytrail: DPTF: Enable mainboard-specific PPCC Reviewed-on: https://chromium-review.googlesource.com/189576 (cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612) baytrail: Add config option for PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189994 (cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5) rambi: Enable PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189995 (cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6) Squashed 13 commits for baytrail/rambi. Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6957 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-20x220: Move to common gpio.h inrastructureVladimir Serbinenko
Change-Id: Ic9734bf2672942a09f2136b0c066f2eda58486d9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7126 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-19amd: rename model_fxx_powernow to powernow.Vladimir Serbinenko
Change-Id: Iee581183f9cd9f5fecd5604536b735f6a04a0f93 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7019 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-10-19e7501: Move to perdev ACPIVladimir Serbinenko
Change-Id: Ic8472745c2ff0c68fd63b51d1a149a11be1650e9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7047 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-19AGESA: Drop board and chipset -specific callout headersKyösti Mälkki
Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7115 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA fam12 fam14 fam15: Sanitize BiosCallOuts headersKyösti Mälkki
Change-Id: Ic08f1f2fdbcf6164eb1a0330f9134da3fdb978d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-19AGESA fam12 fam14 fam15: Use common agesa_readSpd()Kyösti Mälkki
Remove northbridge specific callouts for AGESA_READ_SPD. Move low-level SMBus code to southbridge. Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7113 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA fam15tn fam16kb 00730f01: Add common agesa_readSpd()Kyösti Mälkki
Remove northbridge specific callouts for AGESA_READ_SPD. Move low-level SMBus code to southbridge. Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7112 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19AGESA: Declare callout Fch_Oem_config staticKyösti Mälkki
Change-Id: If5c62b868c4144845d79dc26068c500ab5d26947 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7111 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19ACPI: Allocate S3 resume backup in CBMEM earlierKyösti Mälkki
These allocations are not really part of write_tables() and the move opens possibilities to use CBMEM instead of SPI Flash to restore some parts of system state after S3 resume. Change-Id: I0c36bcee3f1da525af077fc1d18677ee85097e4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7097 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I84ee953196ae9bed3392c2b9bab2e8d9f0d27908 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-18lynxpoint: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Ie8e4fffcec308d1cd5e696605e78671f3ababf40 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18via/vt8454c: Migrate to per-device ACPIVladimir Serbinenko
Change-Id: Ia3f6691ae7c33b5e22010e25a1f01996a594196e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6943 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18i3100: Convert to per-device ACPIVladimir Serbinenko
Change-Id: Id90db4f6ce1a5fb506c81bc3a6010d85b0aa8c43 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18via/vx800: Migrate to collaborative ACPIVladimir Serbinenko
Change-Id: I00d0d0e2556d4cd0553a2b3351ace26bf747ff6a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6944 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18fsp_sandybridge: Move to per-device ACPI.Vladimir Serbinenko
Just took combined sandybridge per-device ACPI patch and applied it on FSP flavour to avoid need of separate tests. Change-Id: I09838cc01ede504416078edcb1c267a11539e714 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18sch: Switch to per-device ACPIVladimir Serbinenko
Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18cimx/sb800: fix pedantic gcc errorRonald G. Minnich
A cast did not work for me, but this variable did. This is one of the many issues with building e3501 I'm running into. Change-Id: Ifb19a17770604f2d63dfef762d08200add77ee34 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/7122 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18intel/i82801bx: Minor log fixes in IDE driverPatrick Georgi
Two issues: 1. without config, there were two NULL derefs 2. output for "Secondary" looked at ide0_enable Change-Id: I34ddbc0f9b27226981ccbc237e3d59e522076d55 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6989 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-18various AMD boards: fix buffer overflowPatrick Georgi
"AMD\t " isn't 8 characters long. Change-Id: I47b2a39d7dca0201b7ee5dfd1f77e0714411257c Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6991 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-10-18e7505: Move to per-device ACPIVladimir Serbinenko
Change-Id: I706891b9408cf14b559ef228766c04e98345ff6e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18i945: Consolidate FADT codeVladimir Serbinenko
Change-Id: I076cba7d21926cabf90d485de50268ae40c435f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7087 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17lenovo/t520: Use native raminit over MRC blobNicolas Reinecke
Native raminit for sandy/ivybridge was introduced in: 7686a56 sandy/ivybridge: Native raminit. An additional current level is needed. Change-Id: Ied73d168045c25d37afa5d9d7073de7f9c6435c7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7098 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-10-17boot/coreboot_tables.h: Use `it is` instead of `it easy` in commentPaul Menzel
Change-Id: I5c8a689a4923175fff1f38847b7cfbbaeeb0ea22 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7092 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17lenovo/t520: Enable wake on LID and Fn keyNicolas Reinecke
Change-Id: Ieb23728ba171733820830e86e77a4c6d8e1cc57d Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7101 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17lenovo/t520: Apply ME workaround for S3 resumeNicolas Reinecke
Without this patch the laptop powers down after resume. Change-Id: Ic6486fd4c4cc55b1ac5695f9d6d83fc2193b7eba Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7102 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17lenovo/t520: fix board infoNicolas Reinecke
Change-Id: Ieeefbe4617ea6c131236d8c94e9990f7b797192b Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7103 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17asus/m5a88-v: Fix southbridge initKyösti Mälkki
This amdfam10 board was by mistake modified with commit b6f3da4 AGESA CIMx: Move late init out of get_bus_conf() Change-Id: I8edf6f7f4cc635d31e7e485e3f6de57ef8ed7b1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-10-17lenovo/t520: Use native LVDS gfx initNicolas Reinecke
As introduced in: 1783a3c ivybridge: LVDS gfx init. The panel on the T520 is a LP156WD1 40 pin LVDS (2 ch, 6-bit). Tx parameters derived from datasheet table. Change-Id: Ib733836e3233a7f14a79f36a27ed36b638e837f5 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7100 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17lenovo/T520: Remove butterfly DSP init.Nicolas Reinecke
It's specific to butterfly. Doesn't do anything on lenovos. Change-Id: I98b7c3199de5d8515bd869936e1b95847321d264 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7099 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Fix ICH spi implementation which reads data from different chips.Philipp Deppenwiese
This patch adjusts the read timeout in order to support flash chips which needs more than 60ms to complete a spi command. This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ). Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-10-17macbook21: Kill empty gpe.aslVladimir Serbinenko
Change-Id: I4ed04ecbc9e11200577cc2b6ede0e05af9f346fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7082 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-10-17macbook21: Kill empty Makefile.incVladimir Serbinenko
Change-Id: I2d946b9d757cc6158ff7f8927a81d7bf03a2e062 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7084 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Kconfig: move SMBIOS related options to SMBIOS table optionStefan Reinauer
Change-Id: I74943d0248f49796b9d31d6ed827c69f8cea13a5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7090 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17macbook21: Kill empty smi.hVladimir Serbinenko
Change-Id: I387bb6154fe432ef2fc5f92faca69e67d7a6370a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7083 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Kconfig: clean up options in top level and device menuStefan Reinauer
Move generic options to the "General Setup" menu. Move device specific options to the "Devices" menu. Change-Id: I514a021305d43f026b24fd3016477300700ed401 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17bd82x6x: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Iea035f80695623e4e8d53eea7e3ec294d868fb5b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7053 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17macbook21: Kill empty mainboard.aslVladimir Serbinenko
Change-Id: I29c7d367df7d1ce911f6cd7ed5e5c56865b41dcc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7063 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17drivers/spi: Add support for Micron N25Q128Scott Radcliffe
Support added for Micron N25Q128 SPI flash, which has the same manufacturer id as ST Micro. Jedec ID = 0x20 0xBB 0x18. Since existing stmicro.c only compares the last device id byte, this flash is mistakenly identified as M25P128, which has ID = 0x20 0x20 0x18. To handle this situation and avoid breaking code for existing devices, a two byte .id member is added. New devices should be added to the beginning of the flash table array with .idcode = STM_ID_USE_ALT_ID and .id = the two byte jedec device id. A 4KB subsector erase capability is added and used for this new device. It requires using a different SPI op-code supported by adding .op_erase member. Previous devices defined in stmicro.c are assigned their original op-code for 64KB sector erase. N25Q128 is now working on a custom designed Bayley Bay based board. Tested by verifying the MRC fastboot cache is successfully (re)written. Note that previous devices were not retested. Change-Id: Ic63d86958bf8d301898a157b435f549a0dd9893c Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7077 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-10-17bd82x6x: Consolidate early native USB initVladimir Serbinenko
Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-17Add board_info for all Google/Intel boards mitting the fileStefan Reinauer
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7072 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17acpi_add_ssdt_pstates: Remove function.Vladimir Serbinenko
Nowhere in database p_state_num is set. So this whole function ends up being a noop. Moreover the offsets used by it are wrong with any optimizing iasl. Remove it in preparation of move to per-device ACPI. Change-Id: I1f1f9743565aa8f0b8fca472ad4cb6d7542fcecb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7012 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17xe7501devkit: Kill unused cmos.layoutVladimir Serbinenko
Change-Id: I04b485945a1830deaf5a695507ea81809edbceeb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7073 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-10-17Fix mismerge of ACPI patchesVladimir Serbinenko
Change-Id: I2a9960861465f4686113213d5e5793333b6274b2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7079 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 15:44:19 +0000