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2013-07-10armv7/exynos5420: Remove the extra reopen when reading SPI.Hung-Te Lin
The workaround of re-opening device in exynos_spi_read has been fixed by the new correct open/close and xfer procedure. It's safe to be removed now. Change-Id: I6b1bf717c916903999a137998a578b0a866829bd Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Apply new implementation for SPI transmission.Hung-Te Lin
Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function. Change-Id: I01ab43509df1319672bec30dd111f98001d655d0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.Hung-Te Lin
The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and only full-duplex mode. To communicate with devices like ChromeOS EC, we need both output (tx) and half-duplex (searching frame header) features. This commit adds a spi_rx_tx that can handle all cases we need. Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Revise SPI open/close/reset procedure.Hung-Te Lin
The original Exynos SPI open/close procedure was copied from U-Boot SPL with some assumptions that only works in SPL stage. For example, it tries to always work in 4-byte transmission mode with only RX data is swapped, and claims a packet for initial address command (and with incorrect size). This commit revises open/close and reset so only the required SPI registers are configured. Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Provide configuration for SPI0~SPI2.Hung-Te Lin
Fill the SPI device parameters for spi_setup_slave on Exynos 5420. Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Change SPI module to standard <spi-generic> interface.Hung-Te Lin
The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard (spi-generic.h) and will be a problem when we want to share SPI drivers. This commit replaces exynos_spi_* by spi_* functions. Note, exynos_spi_read is kept and changed to a static function because its usage is different from the standard API "spi_xfer". Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Clean up unused header and constants in spi.cHung-Te Lin
Remove unused header and constant definition in SPI module. Change-Id: I339e603f48186e4a356e83518b0d0b4c907f11b8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3709 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/exynos5420: Revise SPI device list in cpu.hHung-Te Lin
Add SPI0 and SPI2 to Exynos 5 SPI list, and correct structure names. Also removed the un-enumerated devices (SPI_BASE, base_spi()). Change-Id: Ica6d9a41f9619c8c61eab664d5e988dd4a428e09 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/google: Support ChromeOS EC on SPI bus.Hung-Te Lin
For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface (see spi-generic.h) to exchange data. Note: Only EC protocol v3 is supported for SPI bus. Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/google: Support Chrome EC protocol version 3.Hung-Te Lin
Add the new Chrome EC protocol version 3 to Coreboot. Note, protocol version 3 is not applied on any bus implementations yet. LPC (x86) and I2C (arm/snow) are still using v2 protocol. The first one to use v3 protocol will be SPI bus (arm/pit). LPC / I2C will be updated to v3 only when they are ready to change. Change-Id: I3006435295fb509c6351afbb97de0fcedcb1d8c4 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3750 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/google: Generalize communication protocol support in EC drivers.Hung-Te Lin
Since EC protocol v3, the packet format will be the same for all buses (inclding I2C, SPI, and LPC). That will simplify the implementation in each individual bus driver source file. To prepare for that, we will move the protocol part into crosec_proto.c: crosec_command_proto, with bus driver in callback "crosec_io". Change-Id: I9ccd19a57a182899dd1ef1cd90598679c1546295 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3749 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7/pit: Setup EC on SPI2.Hung-Te Lin
The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10arm/exynos: Correct SPI session commands.Hung-Te Lin
Some initialization / shutdown commands should be paired correctly in a SPI I/O session. For example, setting CS should be enabled and disabled in each read; and the bus width (byte or word) should be configured only when opening / closing the SPI device. Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10AMD: Kconfig cleanupKyösti Mälkki
Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10pit: update I2C4 speed constantDavid Hendricks
Change-Id: I4feabc448945c4664d3114c0c8afdad48338230a Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: i2c: Fix error handling.Gabe Black
The functions which checked the status of a transfer would return success if the bus was no longer occupied, even if it's no longer occupied because the transfer failed. This change modifies those functions to return three possible values, 0 if the transfer isn't done, -1 if there was a fault, and 1 if the transaction completed successfully. Change-Id: Idcc5fdf73cab3c3ece0e96f14113a216db289e05 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Clock the mmc blocks off of the mpll.Gabe Black
The exynos manual suggests hooking the mmc ip blocks to the mpll. They had been set to use a different pll. This changes them over and modifies the divider so that the frequency stays the same. Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Configure the pinmux for the i2c busses that are connected on pit.Gabe Black
Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: use speed parameter in i2c_init() for HSI2CDavid Hendricks
This allows us to set different speeds for each HSI2C bus. Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3701 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Change some clock settings.Gabe Black
This change adjusts some clock settings so that they match U-Boot. There are three different changes. 1. Change the source for psgen from the oscillator clock to the pclk. 2. Change the pll feeding the SPI busses from epll to mpll, as suggested in the manual. 3. Change the SPI prescaller. Change-Id: Ib54a255bc14fc286629dac86db9b8cf8e75a610b Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Fix the way the rate of the input clock for i2c buses is found.Gabe Black
The clock divider was being read from registers incorrectly which meant that the periph rate was wrong. Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3699 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10snow: Add flush to UART driver.Hung-Te Lin
Wait for UART FIFO to be ready. (Credit to dhendrix for finding the bits to test with.) Change-Id: Ib6733e422cbc1c61b942bd90d85f88a3f412d6ff Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3698 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/chromeec: Merge upstream V3 structure and constant definition.Hung-Te Lin
Chrome EC protocol V3 has several new command structure and constants defined. Simply cherry-picking changes from upstream. Change-Id: I7cb61d3b632ff32743e4fa312e0cc691c1c4c663 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. (forward ported from https://gerrit.chromium.org/gerrit/#/c/55554) Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3697 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5250: Initialize USB PHYStefan Reinauer
... this is needed for libpayload to talk to USB devices. Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos: Only compile UART in if serial console is selectedStefan Reinauer
Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Don't try to use CBMEM console in bootblockStefan Reinauer
Otherwise we have to worry about hand off between bootblock and romstage. Too much complexity Change-Id: I89bf8a229dba7e1330accadf9a732d831ebc4827 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Exynos5420: add code to make sure resume will work on DRAM.Ronald G. Minnich
Found during a perusal of u-boot changes. It looks important. For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=56eab63922d2b2380518238ae03e8d69e99af4fe Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3693 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARMv7: Drop duplicate call to bootblock_cpu_init()Stefan Reinauer
This is already called in ARMv7 bootblock_simple.c so we don't want to do it twice Change-Id: I80cb41035b8a77787e04f2ea58a1cd372cea97d8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Simplify early / bootblock console codeStefan Reinauer
Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: Don't leave alignment checking on after the exception test.Gabe Black
Currently, the exception handling code on ARM turns on alignment checks as an easy way to generate an exception for testing purposes. It was leaving it on which disabled unaligned accesses for other, unlreated code running later. This change adjusts the code so the original value of the alignment bit is restored after the test exception. Change-Id: Id8d035a05175f9fb13de547ab4aa5496d681d30c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Replace the snow GPIO indexes with ones for pit.Gabe Black
The GPIOs used by vboot and setting up the display and backlight were still the ones for snow. This change updates them so they're correct for pit. Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Remove the MAX_CPUS option.Gabe Black
The MAX_CPUS option is only used on x86 currently, so there's no reason to have it in the pit config. Change-Id: I270bbfd3aff781d88304791b1d9735777643caab Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop compiling in the max77686 driver on pit.Gabe Black
That part isn't used on pit. Change-Id: I48f3a10f7e6eb89b1e9630d2372b6865b4c12a7f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: Stop calling tps65090 functions until we can call through the EC.Gabe Black
On pit, the tps65090 is connected to the EC and has to be accessed by proxy. Until we have that implemented, this change removes calls to tps69050 which will never succeed, and stops compiling in the driver. Change-Id: I7218f85f9f26623bd13aaaf8ded0638b3b2f874a Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Switch to fixed size types in dmc.h.Gabe Black
The members data structures in dmc.h are intended to have a particular size. Rather than assume that particular types are the right size, we should use types that are guaranteed to be the right size. Also, since the registers are at particular offsets as well, the structures should be packed. Change-Id: I9cc11d7451f92ba3eb85c6be88ecbc62c7a5652d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Revamp the high speed I2C driver.Gabe Black
The previous driver was a bit awkward and not entirely correct. This change primarily replaces the read/write functions with simpler and more robust (hopefully) version. Change-Id: I55f0ad8faec2de520e27577bd6dad9c0118d8171 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3684 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10Samsung CPUs: Unify KconfigStefan Reinauer
For all other CPUs, we unconditionally include the CPU Kconfig files in the CPU directory, not in the vendor directory. Do the same thing for the Exynos CPUs. This allows us to make CPU dependent changes in the directory of that CPU alone. Also, drop some unused Kconfig variables from the Exynos Kconfig files. Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3683 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10arm: Fix memory barrier usage in IO operationHung-Te Lin
The dmb should be executed before reading operations, and before/after writing operations. Change-Id: I572136a2f9a07eb2c38a112f5deeb2de0c0fd46c Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3682 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: update I2C code, add HSI2C/USI supportDavid Hendricks
This updates the low-level I2C code to handle the new high-speed HSI2C/USI inteface. It also outputs a bit more error information when things go wrong. Also adds some more error prints. Timeouts really need to be noted. In hsi2c_wait_for_irq, order the delay so that we do an initial sleep first to avoid an early-test that was kicking us out of the test too soon. We got to the test before the hardware was ready for us. Finally, test clearing the interrupt status register every time we wait for it on the write. Works. Change-Id: I69500eedad58ae0c6405164fbeee89b6a4c6ec6c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10pit: set up the PMIC correctlyDavid Hendricks
This updates the setup_power() function to actually set up the PMIC which is on this board (the MAX77802). Change-Id: I9c6f21f183dacc0bca71277e681e670834412d78 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10max77802: add header for max77802 PMICDavid Hendricks
This adds register offsets and important values for the Maxim MAX77802 PMIC. Change-Id: I3724b82bcb235b6684d2b976876f628f1ffbed3f Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: when setting a GPIO to put, set the value, then the directionRonald G. Minnich
We saw a problem on x86 last year in which setting direction, then value, glitched the output and caused problems. Change this code to set the output, then the direction. Change-Id: I3e1e17ffe82ae270eea539530368a58c6cfe0ebe Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynox5420: Remove the 5250 clock registers and fix the SPI frequency.Gabe Black
The 5420 clock code still had a data structure in it for the 5250 clock registers which was used by some of the clock functions. That caused some clocks to be configured incorrectly, specifically the i2c clock which was running at about 80KHz instead of about 600KHz as configured by U-Boot. Also, the registers and bit positions used to set up the SPI bus were not consistent with U-Boot, and if the bus clock rate were set to 50MHz, a rate which has historically worked on snow, loading would fail. With these fixes the clock rate can be set to 50MHz and the device boots as much as is expected. I haven't yet measured the actual frequency of the bus to verify that it's now being calculated correctly. Change-Id: Id53448fcb6d186bddb3f889c84ba267135dfbc00 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3678 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10PIT: memory setupRonald G. Minnich
Tested and working. Gets us to ramstage. Change-Id: Ib9ea4a6c912e8152246aaf4f1f084a4aa1626053 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: add I2C8-10 to clock_get_periph_rate()David Hendricks
This adds entries for I2C8-10 to giant switch statement in clock_get_periph_rate(). It also eliminates the I2C peripheral's usage of clk_bit_info since it's confusing and error-prone. Change-Id: I30dfc4c9a03fbf16d08e44e074189fb9021edb6d Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10armv7a: Enable native memcpy / memsetStefan Reinauer
The code has been there for quite a while but was never enabled. Change-Id: I4ec3dcbb3c03805ac5c75872614e5d394df667cf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3675 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5420: Implement support for the pinmux as functions.Gabe Black
Change-Id: I5e0ec360597cd95cb6510fb32b04d8931e6a33db Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3674 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10exynos5250: De-switch-ify the pinmux configuration code.Gabe Black
The pinmux code for the exynos5250 was all bundled into a single, large function which contained a switch statement that would set up the pins for different peripherals within the SOC. There was also a "flags" parameter, the meaning of which, if any, depended on which peripheral was being set up. There are several problems with that approach. First, the code is inefficient in both time and space. The caller knows which peripheral it wants to set up, but that information is encoded in a constant which has to be unpacked within the function before any action can be taken. If there were a function per peripheral, that information would be implicit. Also, the compiler and linker are forced to include the entire function with all its cases even if most of them are never called. If each peripheral was a function, the unused ones could be garbage collected. Second, it would be possible to try to set up a peripheral which that function doesn't know about, so there has to be additional error checking/handling. If each peripheral had a function, the fact that there was a function to call at all would imply that the call would be understood. Third, the flags parameter is fairly opaque, usually doesn't do anything, and sometimes has to have multiple values embedded in it. By having separate functions, you can have only the parameters you actually want, give them names that make sense, and pass in values directly. Fourth, having one giant function pretends to be a generic, portable API, but in reality, the only way it's useful is to call it with constants which are specific to a particular implementation of that API. It's highly unlikely that a bit of code will need to set up a peripheral but have no idea what that peripheral actually is. Call sights for the prior pinmux API have been updated. Also, pinmux initialization within the i2c driver was moved to be in the board setup code where it really probably belongs. The function block that implements the I2C controller may be shared between multiple SOCs (and in fact is), and those SOCs may have different pinmuxes (which they do). Other places this same sort of change can be made are the pinmux code for the 5420, and the clock configuration code for both the 5250 and the 5420. Change-Id: Ie9133a895e0dd861cb06a6d5f995b8770b6dc8cf Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3673 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ARM: Tell the linker memset and memcpy are functions.Gabe Black
The memset and memcpy functions are assembled as ARM code, likely because that's the default of the assembler. Without special annotation, the assembler and linker don't know that those symbols are functions which need special handling so that ARM/thumb issues are handled properly. This change adds that annotation which gets those functions working in Coreboot which is compiled as thumb. Libpayload and depthcharge are compiled as ARM so they don't *need* the annotation since it just works out in ARM mode, but it's the safe thing to do in case we change that in the future. We should explicitly select ARM vs. thumb when assembling assembly files to be consistent across builds and toolchains. Change-Id: I814b137064cf46ae9e2744ff6c223b695dc1ef01 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3672 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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