summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2011-10-25T60: use ICS954309 clock driverSven Schnelle
Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/328 Tested-by: build bot (Jenkins)
2011-10-25Add driver for ICS954309 clock generatorSven Schnelle
Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/327 Tested-by: build bot (Jenkins)
2011-10-25i82801gx: Add setting for C4onC3 modeSven Schnelle
If this bit is set, ich7 will enter C4 mode if possible instead of C3. See ich7 specification (LPC controller, Power management control registers) for more details. Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
Change-Id: Idb4b57044808918de343d31519768d0986840f01 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/321 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25ACPI: Add function for writing _CST tablesSven Schnelle
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/312 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25w83627hf: correct typo in ASL include, correct indexed registers and remove ↵Christoph Grenz
unneccesary _PR0 defs Correct a typo in devtree.asl which causes AML processors to fail executing the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero. Also removes an superfluous item in the register IndexField and removes unneccessary _PR0 definitions which could confuse AML processors. Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/296 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25Lenovo H8: Fix h8_set_audio_mute()Sven Schnelle
Logic is inverted (if argument is true, one would expect that mute is enabled) and the wrong bit was used (1 instead 0) Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/334 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25X60/T60: remove superflous h8_set_audio_mute()Sven Schnelle
muting is handled by h8 code, no need to do it here. Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25i82801gx: Add write and read/write block functionsSven Schnelle
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-23i82801gx: Don't set I/O base address to static valueSven Schnelle
Doing it this way will break all subsequent smbus calls, because the smbus code still uses res->base, which points to the old base address. Fix this by allocating a proper resource. Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/325 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-10-23console: support integrated 7-segment displays for POST codesChristoph Grenz
Add a configuration option POST_PORT which defaults to 0x80 and can be redefined by boards which have integrated POST displays on another I/O port. Change post.c to output POST codes to this port instead of 0x80 hardcoded. Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/221 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-23SB800: Hide unused gpp portsKerry Sheh
Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21Extend coreboot table entry for serial portsStefan Reinauer
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21Remove redunancy in KconfigKyösti Mälkki
Socket Kconfig unconditionally selects CPU_INTEL_CORE. Change-Id: I5eb7dd17047a2a031dd7345390d7f5f756055e18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/307 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21sch: strip quotes around cmc.bin filenamePatrick Georgi
This was mentioned several times already, how about we get it in? It avoids cbfstool to fail because path/to/"file" doesn't work. Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/305 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-21Use ntohll where appropriate.Stefan Reinauer
also clean out a local copy of ntohl in yabel. Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/288 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21Add macros for 64bit byte order swappingStefan Reinauer
Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-20T60: Add support for Ultrabay Legacy I/O devices (40Y8122)Sven Schnelle
Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/282 Tested-by: build bot (Jenkins)
2011-10-20i82801dx: Replace romstage printk'sKyösti Mälkki
Patch is required to compile this with romcc. Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/291 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19asrock/e350m1: Enable the superio ACPI device in devicetree.cbPeter Stuge
This makes the power_on_after_fail NVRAM option work correctly. Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/292 Tested-by: build bot (Jenkins)
2011-10-19IOAPIC: fix bitmaskKyösti Mälkki
APIC ID is bits 27..24, not 19..16. Change-Id: Ib53a480bf4328901094ca2c4713e8317321962a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/299 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19sconfig: check whether component directory actually existsStefan Reinauer
and add drivers/generic/generic back (empty), since it is used by many devicetree.cb files. Without this patch typos in component names in devicetree.cb cause the component to be silently ignored. Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/270 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19Drop eh_frame instead of moving it into the image.Stefan Reinauer
That's what SeaBIOS does, too, and it works just fine. Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/269 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-19I945: replace #if defined() by #ifSven Schnelle
config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/293 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18Append logical PME/GPIO device. Fix MPU device number.Kyösti Mälkki
A mainboard may require configuration of the superio pins to fully support some features. Things like A20# gate, leds, fans, infra-red and bootstrap jumpers may be configured and controlled through the logical PME device. Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/289 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
As new microcode files were included, the table was not updated with families 0f25 and 0f26. Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/290 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-17Fix our CMOS checksum algorithm so it matches what /dev/nvram expectsStefan Reinauer
Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it! Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1 Signed-off-by: Vadim Bendebury <vbendeb@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/279 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17rework RTC driver output to make it more consistent.Stefan Reinauer
Also add a meaningful define (Not hooked up in Kconfig, that might or might not follow) Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/278 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17Re-worked devicetree.cb for DL145 G1Oskar Enoksson
After a lot of experimentation this commit improves some hardware features that were not recognized or incorrectly configured before. The only thing not tested is SCSI-option board (I dont have one). Misleading errors in comments have been corrected. (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade which was supported in early versions of coreboot but was dropped for some reason.) Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e Reviewed-on: http://review.coreboot.org/237 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-17Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson
First issue fixed: For multi-socket CPU the current implementation emitted Processor objects for cores in the first CPU only. This commit fixes the bug by really emitting one Processor object for each core. However, the unlikely case of mixed CPU models is still not handled correctly. Second issue fixed: One loop was wrong in case a processor in the table declares no P-states at all. The rewritten loop is safe. Some possibly dangerous array lengths were also fixed. Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV according to the BKDG. The current implementation always set it to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS. Fourth issue: If a processor without PowerNow! support was inserted in a system with coreboot configured with SET_FIDVID then the boot process hanged mysteriously and very early. Apparently because init_fidvid_ap tampers with non-existing registers. This commit fixes the bug by bailing out from init_fidvid_ap if PowerNow! capability is missing. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417 Reviewed-on: http://review.coreboot.org/239 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
According to Rudolf Marek putting a memory instruction between the CR0 write and the jmp in protected mode switching might hang the machine. Move it after the jmp. There might be a better solution for this, such as enabling the cache, as keeping it disabled does not prevent cache poisoning attacks, so there is no real point. However, Intel docs say that SMM code in ASEG is always running uncached, so we might want to consider running SMM out of TSEG instead, as well. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec Reviewed-on: http://review.coreboot.org/283 Reviewed-by: Sven Schnelle <svens@stackframe.org> Tested-by: build bot (Jenkins)
2011-10-15use byteorder.h instead of implementing another byte swap functionStefan Reinauer
Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/277 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/276 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15cbfs_and_run_core() is not part of the API, make it static.Stefan Reinauer
It's only used in cbfs_and_run.c Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/273 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2011-10-15reformat Makefile.bootblock.inc (>80 lines per char)Stefan Reinauer
Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/274 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6Stefan Reinauer
Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/268 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix compilation of AMD GX2 northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/267 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix compilation of VIA CN700 northbridge code with gcc 4.6Stefan Reinauer
Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14fix compilation of intel/sch northbridge code with gcc 4.6Stefan Reinauer
Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/264 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-14Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6Stefan Reinauer
Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/263 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-13Prevent build breakage without consoles enabledStefan Reinauer
If all console types are disabled, coreboot will fail to compile because static code is unused. This patch fixes the issue. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2 Reviewed-on: http://review.coreboot.org/260 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Load an IDT with NULL limitStefan Reinauer
Load an IDT with NULL limit to prevent the 16bit IDT being used in protected mode before c_start.S sets up a 32bit IDT when entering ram stage. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e Reviewed-on: http://review.coreboot.org/259 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix compilation of x86emu with gcc 4.6.xStefan Reinauer
gcc 4.6 complains about unused but set variables in x86emu. Particularly some variables are always set but only used in debug mode, or when FPU support is enabled. Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/258 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix native x86 option rom initializationStefan Reinauer
- Intel option roms want an initialized i8259 or they will throw an exception 6. This should be done in the southbridge code, but that is executed much later than the VGA init, so initialize the i8259 in src/devices/oprom/x86.c. In the long run this will allow getting rid of some of the ugly hacks in some AMD boards' romstage.c - Don't overwrite the mode when copying mode info information back from 0x600. Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/257 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13refactor vesa mode setting code and bootsplash codeStefan Reinauer
- adds possibility to set a vesa mode without showing a bootsplash - make bootsplash / mode setting code available in real mode. Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/256 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Refactor option rom initialization code in coreboot.Stefan Reinauer
- move int15 handler out of the generic code into the mainboard directories of those mainboards that actually use it. - move vbe headers to vbe.h - move function prototypes used in native oprom code to x86.h Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/255 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Enable/fix compilation of i8254 code in ram stage.Stefan Reinauer
Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/254 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Fix romstage creation with gcc 4.6 and CAR targetsStefan Reinauer
newer gcc versions generate ".section .text" instead of just ".text" in their assembler output. This patch makes sure that we don't end up with a superfluous ".section" that makes the build fail. Add -Wno-unused-but-set-variable to CFLAGS if the flag exists. Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/252 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-05 00:44:07 +0000