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2015-03-05rush_ryu: Add new mainboardAaron Durbin
This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05tegra132: add support for TZ carve-outAaron Durbin
The TrustZone carve-out needs to be taken into account when determining the memory layout. However, things are complicated by the fact that TZ carve-out registers are not accessible by the AVP. BUG=chrome-os-partner:30572 BRANCH=None TEST=Built and booted to end of ramstage. Noted that denver cores can read TZ registers while AVP doesn't bother. Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494 Reviewed-on: http://review.coreboot.org/8593 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-05coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at initFurquan Shaikh
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR registers should be done with proper bitmask. BUG=None BRANCH=None TEST=Compiles successfully and verified that the RES bits are preserved across register writes. Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207815 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9 Reviewed-on: http://review.coreboot.org/8592 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-03-05t132: handle carve-outs for addressable memoryAaron Durbin
The carve-out regions need to be taken into account when calculating addressable memory because those regions aren't accessible from the main cpu. The additional exposed functions are to accommodate adding resources during ramstage resource reading. The TZ (trust zone) region is empty for now until more documentation is provided on determining its location. BUG=None TEST=Built and booted through attempting payload loading. MTS carve-out is taken into account programmatically. Original-Change-Id: I3301b2a12680ad79047198ada41f32eb1b7fa68b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207585 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 15b9c74dd1ef5bfb1fd7c6dab50624f815658e14) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I46d54dbbb8e102fc70ab34bc4bbd2361ef1ea504 Reviewed-on: http://review.coreboot.org/8591 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05t132: Enable cbmem console supportAaron Durbin
Enabled CBMEM support for t132 platforms. Some of the existing code is moved around to avoid dependencies in the other stages that need it. BUG=None BRANCH=None TEST=Built and booted a rush with cbmem support. Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207163 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b Reviewed-on: http://review.coreboot.org/8589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05t132: bring up 64-bit denver coreAaron Durbin
The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05mainboard/siemens/mc_tcu3: Add new mainboard.Werner Zeh
This mainboard is based on Intel's Bayleybay board which uses Bay Trail CPU with Intel FSP. It has one USB3.0 interface, 4 USB2.0 interfaces, up to two Ethernet ports and a LVDS connection for LCD panels. The board is equipped with 512 MB of DDR3 in a memory down configuration. This board boots into Ubuntu/Lubuntu 14.10 using SeaBIOS, but other OSes should work as well (but are not tested). It has a version.hex file which is needed for our OS and has no hardware functionality. Change-Id: I94401bbd1d61ec69703de38ae1bc97969c5d979e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8430 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05fsp_baytrail: Add I2C driverWerner Zeh
Add a driver wich can handle the internal I2C controllers of Baytrail SoC. This driver is not suitable for the SMBus controller. Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8401 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05fsp_baytrail: Add new microcode for Bay Trail MWerner Zeh
Add a new microcode for Bay Trail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has been added (I or M/D) which allows to use only the really needed microcode for a given CPU type. Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8399 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variableAlexandru Gagniuc
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8498 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04arm64: Set 16 byte alignment and ramstage start addressAaron Durbin
To align with arm use the RAMSTAGE_BASE Kconfig option for start of ramstage. Also, use 16-byte alignment for the start and end of the sections. 4 bytes were previously used, but it definitely seems more appropriate to at least have the heap handing out 16-byte aligned pointers. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through attempting to load payload Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207432 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550 Reviewed-on: http://review.coreboot.org/8588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04arm64: remove assembly code string functionsAaron Durbin
Inconsistent progress was observed running ramstage. It was determined that the hand-coded assembly functions were causing issues. Some of the comments seems suspect about the hardware taking care of alignment. The prudent thing to do is to use the C ones. Optimization can come later after maturity. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted to attempting to payload Original-Change-Id: I4137adf9b36b638ed207e4efd57adaac64c6a6c1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207431 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 2762e478c6b59dd30c59aa87a922d0f78c00c0c4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id3196b0c2bf41a21db31f999ba437d118875a236 Reviewed-on: http://review.coreboot.org/8587 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-04arm64: use one stage_entry for all stagesAaron Durbin
Ramstage needs an assembly entry point for setting up the initial state of the CPU. Therefore, a function is provided, arm64_el3_startup(), that bootstraps the state of the processor, initializes the stack pointer, and branches to a defined entry symbol. To make this work without adding too much preprocessor macro conditions provide _stack and _estack for all the stages. Currently the entry point after initialization is 'main', however it can be changed/extended to do more work such as seeding the stack contents with tombstones, etc. It should be noted that romstage and bootblock weren't tested. Only ramstage is known to work. BUG=chrome-os-partner:29923 BRANCH=None TEST=Brought up 64-bit ramstage on rush. Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207262 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949 Reviewed-on: http://review.coreboot.org/8585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04arm64: ensure vital sections aren't garbage collectedAaron Durbin
The driver structures live in special sections which have no direct reference to the symbols. Therefore, when garbage collecting sections in the linker the drivers are tossed out resulting in no drivers being linked into ramstage. Fix this by adding the KEEP() directive to those special sections. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and noted console starts working in ramstage. Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207261 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4 Reviewed-on: http://review.coreboot.org/8584 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04coreboot t132: Stack init re-workFurquan Shaikh
1) In order to avoid stack from overflowing during ramstage decompression, initialize stack right at the beginning of romstage. 2) Declare different Kconfig options for stack at each stage. 3) Provide a macro that does stack seeding if required and calls appropriate function. BUG=None BRANCH=None TEST=Compiles and runs successfully on rush. Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206880 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd Reviewed-on: http://review.coreboot.org/8583 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04rush: PMIC: initial AS3722 PMIC writes for RushTom Warren
Still waiting on VDD_CPU value, etc. from board guys, but this is a start. BUG=None BRANCH=None TEST=Built and flashed rush, saw 'PMIC init done' string OK. Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206412 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2 Reviewed-on: http://review.coreboot.org/8582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: kick off core complex after loading MTS microcodeAaron Durbin
Once the MTS microcode is loaded the core complex can be directed to decode the MTS and start running. The cores, however, won't start executing until instructed to do so. BUG=chrome-os-partner:29222 BRANCH=None TEST=Built, booted, ran. Noted it took about 920ms for the core complex to decode and handshake back. Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206075 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> (cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e Reviewed-on: http://review.coreboot.org/8581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04coreboot memrange: Two changes for zero size or empty memrangeFurquan Shaikh
1) Add check for zero size in memrange. 2) Add public memrange_init_empty function to allow initializing only the memrange structure without filling in device resources BUG=None BRANCH=None TEST=Compiles and runs succesfully for rush MMU memranges. Original-Change-Id: I8e4d864cbc9a770cd208f8a9f83f509dc7ace894 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208957 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5c42301c2a51a1a2a29ef58012f210d03bd37f94) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8d63abb15efda74270ef6fa3c0df55c05659595d Reviewed-on: http://review.coreboot.org/8597 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-04t132: load MTS microcodeAaron Durbin
The armv8 cores need to have microcode loaded before they can be taken out of reset. Locate and load the MTS microcode at the fixed address of 0x82000000. The ccplex, once enabled, will decode and transfer the microcode to the carveout region. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and ran. Confirmed dump of MTS region after loading code. Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206290 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df Reviewed-on: http://review.coreboot.org/8580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04Add stage information to coreboot bannerStefan Reinauer
As a convenience, print the actual stage name when entering a stage. Also unify the banner between bootblock / romstage and ramstage. No reason for two different occurences. Instead of this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting... you will see this: coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting... [..] coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting... Roughly based on: https://chromium-review.googlesource.com/199671 Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8578 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-04rush: enable 128MiB MTS carveout below top of DRAMAaron Durbin
The recommended settings for the size of the MTS region is 128MiB. Therefore, provide this region 128MiB below the top of DRAM for each configuration. BUG=chrome-os-partner:29922 BRANCH=None TEST=Built and noted MTS carveout region at expected location. Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/206291 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I369a3897e31f3126d031d3582f52f9892350f658 Reviewed-on: http://review.coreboot.org/8579 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: Replace fallback with CONFIG_CBFS_PREFIXMarc Jones
Use the Kconfig value to load the name of the stage instead of the hard-coded fallback stage. (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b Reviewed-on: http://review.coreboot.org/8576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04t132: Add shared romstageAaron Durbin
There's no reason to duplicate code in the mainboards. Therefore, drive the flow of romstage boot in the SoC. This allows for easier scaling with multiple devices. BUG=None BRANCH=None TEST=Built and booted to same place as before. Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205992 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19 Reviewed-on: http://review.coreboot.org/8575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add dram init codeFurquan Shaikh
Add support for initializing dram within romstage. This is an essential before we move to the armv8 core. BUG=None BRANCH=None TEST=Compiles succesfully for rush. Tried writing to and reading value from the base of sdram and it worked fine. Also tested with primitive_memtest CL: https://chromium-review.googlesource.com/#/c/186309/5 Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205823 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4baface2c109ca74f85f43a25508677c46c64159 Reviewed-on: http://review.coreboot.org/8574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot rush: Add support for basic romstageFurquan Shaikh
Add basic romstage support for rush. Since, dram init needs to be done before we can jump to armv8 core, romstage will run on armv4 core as well. Thus, correcting the compiler selection options. BUG=None BRANCH=None TEST=Compiles successfully for rush. Prints romstage banner and initial printk Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205763 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a Reviewed-on: http://review.coreboot.org/8573 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04coreboot t132: Enable loading of romstage from CBFS mediaFurquan Shaikh
Add proper Kconfig options and initialize cbfs media to enable loading of romstage BUG=None BRANCH=None TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer for romstage Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205762 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78 Reviewed-on: http://review.coreboot.org/8572 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132: Remove init pllx for nowFurquan Shaikh
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source for the CPU cluster). So, remove the init call for pllx. This needs to be added later when required. Also, add a few more printks to display the progress. BUG=None BRANCH=None TEST=Compiles successfully for rush. Print messages seen on serial console. Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205680 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81 Reviewed-on: http://review.coreboot.org/8571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04coreboot t132,rush: Add mainboard specific bootblock_initFurquan Shaikh
Pull in mainboard specific bootblock_init function from nyan into rush. Additionally, pull in all files required for proper compilation of rush after adding the bootblock_init function BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205583 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795 Reviewed-on: http://review.coreboot.org/8570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04cpu/amd/model_10xxx: Documentation updateTimothy Pearson
Change-Id: Ic29009be42ef77261a3b535327cf5c12761023c1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8497 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04cpu/amd/model_10xxx: Refactor model detection to reduce code duplicationTimothy Pearson
Moved mctGetLogicalCPUID() to a separate file and made it available in both romstage and ramstage. Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8499 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-03coreboot t132: Add clock.c to all three stages of corebootFurquan Shaikh
Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code for enabling armv8 core is not included yet. clock_init added to bootblock.c BUG=None BRANCH=None TEST=Compiles successfully for rush. Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205581 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I688e1e1373dea26557a84507a8e92d3055862801 Reviewed-on: http://review.coreboot.org/8569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-03northbridge/amd/amdmct: Add revision D to K10 revision mask listTimothy Pearson
Change-Id: Ib5f87bdc50c0bca370a636218d3b5d4cc9157c12 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8501 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-02coreboot arm64: Correct cache function namesFurquan Shaikh
Correct function names to make them consistent with generic calling name BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205582 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16668529527224fca3086ee88955d29e3a268516) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317 Reviewed-on: http://review.coreboot.org/8469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02coreboot arm: Define function for setting cntfrq registerFurquan Shaikh
Define functions for setting cntfrq register in arm and arm64 arch. This allows SoCs to set this register independently of the architecture being used. BUG=None BRANCH=None TEST=Compiles successfully for nyan and rush Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205580 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a Reviewed-on: http://review.coreboot.org/8468 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02tegra132: Enable bootblock support in tegra132 including UART supportFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203143 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3) This cherry-pick was modified to match the tegra124 uart.c, which uses the idx and base address calculations instead of Kconfig settings. This driver could use the 8250MEM driver when the ARM vs x86 IO calling convention is worked out. Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-01devicetree: Drop redundant scan_bus() opsKyösti Mälkki
Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8533 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01devicetree: Drop dummy root_dev opsKyösti Mälkki
This is just dead code. Should we decide that we want some of these calls made, they would be implemented in the mainboard context. Change-Id: I1f097c8da722f3afab9aa1c80b96590c7ca457d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8532 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01AGESA fam16: Drop HyperTransport scanKyösti Mälkki
Already done for fam15tn/rl. Change-Id: Id74ca13610a4ef407c866a4419139287413078a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8531 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28cpu/intel: (non-FSP) Remove microcode updates from treeAlexandru Gagniuc
Now that we use the microcode updates in the blobs repository, remove them from the main repo. Since the microcode updates are blobs, it makes more sense to ship them in the blobs repo rather than the main one. The update-microcodes.sh script is also deleted, as a more current version resides in 3rdparty. Change-Id: Iee74a3ede3b5eb684ef0386d270120e70173c1b4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4531 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28cpu/intel (non-FSP): Use microcode from blobs repositoryAlexandru Gagniuc
Now that microcode has been added to blobs, use that one instead of the one included in the tree. Microcode from the tree will be removed in a subsequent patch. Since the microcode updates are blobs, they belong in the blobs repository. This change may introduce a build failure if the "Generate from tree" microcode option is selected, but the blobs repository is not enabled. We have to live with this for now, until microcode is moved to blobs for all CPUs, at which point we may adjust Kconfig accordingly. Leave the FSP cpu alone for now, as that will need approval from SAGE. Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4530 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-27x86: Fix pointer arithmetic regressions from MMIO changesKevin Paul Herbert
During the development of commit bde6d30 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer), there were several iterations and patterns tried. An intermediate pattern was the use of u32 pointers, and division by sizeof(u32). Some of these did not get properly changed to pointer types of length 1, causing a regression in the Intel Ibex Peak SATA driver, fixed in commit 9b5f137 (Intel ibexpeak: Fix SATA configuration). Other regressions of this pattern are fixed here. I audited all changes to u32 types, and the other ones are safe. Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Reviewed-on: http://review.coreboot.org/8530 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-26mainboard/asus/kfsn4-dre: Enable W83793 fan controllerTimothy Pearson
The Winbond W83793 fan controller is not automatically configured correctly on power application, leading to abnormal, and in some cases random, fan behaviour. This commit enables the controller and sets sane default values. TEST: Booted mainboard and verified that the correct number of fan speed sensors were visible from hwmon under Linux. Also verified that, unlike before, the CPU fans were running at a high enough speed to properly cool the CPUs. Verified the 8 fan outputs under direct control of the W83793 device. Verified voltage and temperature sensors and limits via output of the 'sensors' command. Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8503 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-26drivers/i2c/w83793: Use devicetree.cb to set additional valuesTimothy Pearson
This allows devicetree.cb to set: Minimum PWM values Temperature sensor source Voltage sensor high/low limits Fan pin routing Default PWM values Manual PWM values per-fan Change-Id: I3a321406a26ae01a121289d24b41c9f988dd6f30 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8502 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-25rush: Correct version field to match t132Aaron Durbin
The version field for t132 cpus is 0x00130001. Update it to the correct version. BUG=chrome-os-partner:29882 BRANCH=None TEST=Built and was able to see serial with subsequent changes. Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205435 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a Reviewed-on: http://review.coreboot.org/8467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25coreboot arm64: Add library for system accessFurquan Shaikh
Add support for library functions required to access different system registers: 1) PSTATE and special purpose registers 2) System control registers 3) Cache-related registers 4) TLB maintenance registers 5) Misc barrier related functions BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203490 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb) armv8: GPL license armv8 lib BUG=None BRANCH=None TEST=Compiles successfully. Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250950 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e) Get the library and the GPL license in a single commit. Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d Reviewed-on: http://review.coreboot.org/8465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-25tegra124: Clean up ARM UART driver buildMarc Jones
CONFIG_CONSOLE_SERIAL_UART has been updated to CONFIG_DRIVER_UART. The UART may be used for more than serial console. Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25arm64: Remove early_console.cMarc Jones
The early_console.c file isn't used or built. It has been replaced by the generic uart and console drivers. Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8529 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`Paul Menzel
Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`). Therefore remove the explicit selection of that Kconfig option. Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25intel/broadwell: free local heap objectPatrick Georgi
No real harm done (thanks to our free() implementation), but let's do it right. Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8511 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-25amd/sb600: Fix NULL test after use issuePatrick Georgi
Change-Id: Icecbcc1dee837ecfe0dd52bade3b83fdcdd15bad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8513 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 19:16:53 +0000