summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2021-02-10mb/google/volteer/var/voxel: Add settings for noise mitgationSheng-Liang Pan
Enable acoustic noise mitgation for volteer platforms. BUG=b:179328166 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-10soc/intel/{cnl,skl}: Add alignment check for TSEG base and sizeBenjamin Doron
Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG base and size) to remaining SoCs. Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/google/volteer: Enable external bypass, clkgate & phygateShreesh Chhabbi
This change sets the soc config options for external_bypass, external_clk_gate and external_phy_gate. BUG=b:177821896 TEST=Build coreboot for volteer Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi
This change uses the following information to determine the appropriate S0ix states to enable as per PDG document: 607872 for TGL UP3 UP Rev2p2 (section 10.13): 1. SoC - UP3 v/s UP4 2. H/W design - external phy gating, external clk gating, external bypass 3. Devices enabled at runtime - CNVi, ISH In some cases, it is recommended to use a shallower state for S0ix even if the higher state can be achieved (e.g. with external gating not enabled). This recommendation is because the shallower state is determined to provide better power savings as per the above document. Deepest state expected on tigerlake up3 based platforms is S0i3.2. BUG=b:177821896 TEST=Build coreboot for volteer. Verify that deepest S0ix substate that is enabled is S0i3.1 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/google/zork: devicetree: Fix typo in *Coprocessor* in commentPaul Menzel
Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants) Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-10acpi: Fix Coverity Scan reportLijian Zhao
Fix the issue that return value "r" in line 534 will get overwritten problem. BUG=CID 1445995 TEST=Build sucessful and boot up in QEMU Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Icf760b142cfecfed7c929c15ad190ac74df027b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-10src: Remove unused <boot_device.h>Elyes HAOUAS
Change-Id: Idbb4d72e1ba620f71e8bf882d434c103cb422615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50201 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Set Port C VREF as per EEPROM configAngel Pons
Configure Port C VREF according to the settings in the EEPROM. Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Configure 'internal audio'Angel Pons
Implement `mainboard_azalia_program_runtime_verbs` to configure the Realtek ALC888 codec according to the settings in the EEPROM. The encoding of the `internal_audio_connection` field is: 0: Disabled 1: Front HP out 2: Internal speaker Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10device/azalia_device: Add mainboard hook to program codecsAngel Pons
On some mainboards, codec configuration depends on settings that are only known at runtime, which is impossible to specify using one verb table. Add an optional `mainboard_azalia_program_runtime_verbs` hook where mainboards can program runtime-dependent codec verbs. Change-Id: I7efeba5c26051aeb5061cce191ace08c304a6c70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10device/azalia_device: Add function to program a verb tableAngel Pons
On some boards, Azalia configuration depends on config settings that are not known at compile-time. Expose a function to program a verb table, to be used in subsequent commits. Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10device/azalia_device.c: Correct print formatAngel Pons
The type of `verb_size` is unsigned, thus use `%u` to print its value. Change-Id: I2b353b940e881dc8b5f0b902509d97d89c997a70 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-10nb/intel/x4x: Correct DDR3 turnaround tableAngel Pons
Comparing against MRC, looks like the values for TA3 and TA4 are backwards. All of them. Thus, correct the tables accordingly. Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works. Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4 Tested-by: Michael Büchler <michael.buechler@posteo.net> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Büchler <michael.buechler@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/prodrive/hermes: Set mb_hda_amp_enable based on cfgPatrick Rudolph
Change-Id: I13c2ece729128fe245de88c0d36ce7b4bcaf6b6d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/prodrive/hermes: Drop reset functionsPatrick Rudolph
The reset GPIOs are already configured in bootblock. Drop the unused ramstage code. Change-Id: Ic99fcae2a3f00be7eebd7be618df838522dac69f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10mb/siemens/mc_apl2: Switch I2C bus for RX6110SAMario Scheithauer
With a new HW revision of this board, the connection of the external RTC RX6110SA was changed from I2C bus 0 to I2C bus 3. Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_utilFelix Held
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd: Move global_smi_enable to common/blocks/smi/smi_utilFelix Held
Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd: Move soc_route_sci to common/blocks/smi/smi_utilFelix Held
Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42988 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/picasso: Move APM_CNT_SMMINFO callsiteKyösti Mälkki
Triggering SMI is not part of the semantics of global_smi_enable(), so move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3 check we don't get PSP warnings/errors during resume, so we can drop the workaround introduced in commit 5dbe45e0f5608794e03634aed28530ddb2ab9ac5 in this patch. Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/gardenia: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I8c8845ed6eb466acff568247184c6ad6b186e9ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46145 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/olivehill: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Icacd8c8a7b5604354a7fd04ed73ecb3bbc86e669 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46147 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/jetway/nf81-t56n-lf: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are same. Change-Id: I16eceec980c10e77f2a0aec9a420437d03fc2352 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46187 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/persimmon: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I492118c9287b5853e8784a6de6bc514e97c93e96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46150 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/south_station: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I52c33679fbb7e9807423fc0fcc470e54105013db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46151 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/union_station: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are identical. Change-Id: I8127b5b22e2822f4ace07c28409e501c3fcb309b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46153 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10mb/amd/inagua: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I0ee0d2b83cbfd81fab43eec255bcc214b9543f82 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46146 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10sb/amd/common/acpi: Convert 'sleepstates.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I16919a0fd5a78d666dc7003d4e495fd41c24613d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/{agesa,pi}hudson/acpi: Convert 'pci_int.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I1a382eaf122e40aeaefedf88425749616a2090d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10mb/gizmosphere/gizmo: Convert to ASL 2.0 syntaxElyes HAOUAS
Built for gizmosphere/gizmo (Gizmo), it provides identical dsdt.dsl file. Change-Id: I8647080cda7715d323d38f93c33176dfe9608652 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/{agesa,pi}hudson/acpi: Convert 'AmdImc.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ica6998026031e1b3d7286ce74a2334237d29ac74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10mb/lippert/frontrunner-af/acpi/sata.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ife718dcec765d3b2861bce16f9ca2b6355166800 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/agesa/hudson/acpi/fch.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I8903450b505701e1fd62c1a70b896a4dfb37d5a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-10sb/amd/{agesa,pi}/hudson/acpi: Convert 'audio.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I976b4c2e2aa878d8b591c3e416ffb76d7a699b39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45863 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09Revert "soc/amd/picasso: Change GPIO _HID to AMDI0030"Martin Roth
This reverts commit 75f6ab35ffefec72e343175686d7ef45b30b0939. Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized. BUG=b:179320024 TEST=WP pin shows up properly in crossystem after reverting this change. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0850fd085b5ee70522752633900f69d4d3732321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09mb/google/zork: update USB 3 controller phy Parameter for dirinbozKevin Chiu
Recommendation from SOC to config IQ=8 for U3 port0, vboost for all U3 ports for passing ESD pin test. BUG=b:175192931 BRANCH=zork TEST=1. emerge-zork coreboot 2. run U3 SI/ESD pin test => pass Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-09soc/amd/picasso/cpu: move set_cstate_io_addr to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/picasso/cpu: move get_cpu_count to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/cezanne: Add root_complexRaul E Rangel
This is a copy/paste of picasso with a few things removed. With this change we can jump into depthcharge. Allocated resources: PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6 PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b TEST=Boot majolica and see depthcharge finally loading: Starting depthcharge on MAJOLICA... new_rt5682_codec: chip = 0x1A Looking for NVMe Controller 0x3004cac8 @ 00:01:07 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/cezanne: add empty CPU driverFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I54299cadae4cb562e04a16c3b8e051c9c454db79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09security/vboot/bootmode: Add weak fill_lb_gpiosRaul E Rangel
This change allows VBOOT to build when the mainboard hasn't implemented any of the VBOOT functions yet. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I42ca8f0dba9fd4a868bc7b636e4ed04cbf8dfab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50341 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/cezanne: Enable early LPC support in bootblock stageZheng Bao
Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncarFelix Held
The same functionality is needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-09vc/amd/fsp/cezanne: add FspGuids.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/picasso/memmap: drop __SIMPLE_DEVICE__Felix Held
No PCI or PNP functions are used in here. TEST=Timeless build results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/stoneyridge/memmap: drop __SIMPLE_DEVICE__Felix Held
No PCI or PNP functions are used in here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I46851656db1f1866a82f06ceab67c93019cc6af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-09src: Add missing <cbmem.h>Elyes HAOUAS
Change-Id: I75a816c594b326df8a4aa5458bb055fca35e1741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd,intel: Drop s3_resume parameter on FSP-S functionsKyösti Mälkki
ACPI S3 is a global state and it is no longer needed to pass it as a parameter. Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki
Hide the detail of allocation from cbmem from the FSP. Loading of a BMP logo file from CBFS is not tied to FSP version and we do not need two copies of the code, move it under lib/. Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-19 23:00:14 +0000