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2019-04-12soc/intel/cannonlake: Do not use XIP_ROM_SIZEFurquan Shaikh
XIP_ROM_SIZE Kconfig option isn't used on Cannon Lake and family. Thus, this change selects NO_FIXED_XIP_ROM_SIZE to indicate to build system so that romstage can be placed in less rigid manner. BUG=b:129802811 Change-Id: I5f3786396246c89b1039ba1b6b332a32e6a0345d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-12mb/google/hatch: Skip UART0 config in FSPFurquan Shaikh
UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=b:130325418 Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2019-04-11drivers/spi: Move M25Pxx commands to spi_winbond.hFrans Hendriks
Move Winbond M25PXX command values to spi_winbond.h file. The command values will be used for programming SPI contoller of Intel Braswell, using this include file. Update winbond.c file with coreboot header. BUG=N/A TEST=Facebook FBG-1701 with flashrom Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11drivers/intel/fsp1_1: Configure UART after memory initFrans Hendriks
FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11mb/asrock/h110m: Add virtual LDN for SuperIO to DTMaxim Polyakov
Adds virtual logical devices numbers for the Nuvoton (NCT6791D) SuperIO to the devicetree. Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-11google/kukui: Add variant 'Krane'Hung-Te Lin
Add the new configuration 'Krane' that will need at least its own EC. There's currently no difference in coreboot side. BUG=b:130011505 TEST=make menuconfig; make -j # select board=Krane BRANCH=None Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11nb/intel/i945: Fix ich7_setup_root_complex_topologyElyes HAOUAS
Element Self Description register (ESD) [23:16] is R/WO, so let write the ESD.CID when we start ich7_setup_root_complex_topology. This value is also used to program the R/WO 'Target Component ID' registers of RPxD and HHD. Once it is done, no need to rewrite on them as they become RO. (For more information, please see ICH7 datasheet page 271.) Tested done on 945G-M4 using printk before and after writing. Before this change, writing on those registers had no effect: ESD: 0x0104: 0x00000802 ULD: 0x0110: 0x00000001 ULBA: 0x0118: 0x00000000 RP1D: 0x0120: 0x01000003 RP2D: 0x0130: 0x02000003 RP3D: 0x0140: 0x03000002 RP4D: 0x0150: 0x04000002 HDD: 0x0160: 0x0f000002 RP5D: 0x0170: 0x05000002 RP6D: 0x0180: 0x06000002 Using this patche, those R/WO get the "right" values. i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR. ESD: 0x0104: 0x00020802 ULD: 0x0110: 0x01010001 ULBA: 0x0118: 0xfed18000 RP1D: 0x0120: 0x01020003 RP2D: 0x0130: 0x02020003 RP3D: 0x0140: 0x03020002 RP4D: 0x0150: 0x04020002 HDD: 0x0160: 0x0f020002 RP5D: 0x0170: 0x05020002 RP6D: 0x0180: 0x06020002 Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30993 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11mb/google/sarien: Reserve gpio pins for D3 cold controlEric Lai
Based on HW change, reserve gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD BUG=b:123263562 TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11mb/google/sarien: Change GPIOs to avoid leakage during S0iXRoy Mingi Park
Three GPIOs are not being used and this change will save 2-3mW power during S0iX and this power saving is only for Arcada BUG=b:129990365 TEST= Measure total platform power during S0iX from Arcada Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11nb/intel/{gm45,i945,x4x}: Correct array bounds checksJacob Garber
There will be an out of bounds read if the index is equal to the array size. Fix the checks to exclude this case. Found-by: Coverity Scan, CID 1347350, 1347351 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I5b4e8febb68dfd244faf597dfe5cdf509af7a2ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/32244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groupsAamir Bohra
This implementation corrects the GPE DWx mapping for GPIO groups. The assignments is done in GPIO MISCFG register for all GPIO communities. And configures the which GPIO communities get register as Tier1. BUG=b:121212459 TEST: Verified the GPIO MISCFG is getting set as per updated map. Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32175 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.Tim Wawrzynczak
WiFi enable signal was configured and driven as active-high, but the signal is |To start the server in this Emacs process, stop the existing actually active-low BUG=b:130196983 BRANCH=none TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff". Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flagJoel Kitching
The value of "write protect" GPIO shall be read in depthcharge, and the flag shall be set there instead. BUG=b:124141368, b:124192753, chromium:1556855 TEST=Build locally CQ-DEPEND=CL:1556855 BRANCH=none Change-Id: I4d24a057b1385244a836a67c565ee6726a894fdc Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11chromeos: clean up "recovery" and "write protect" GPIOsJoel Kitching
The "write protect" GPIO's cached value is never actually read after entering depthcharge. Ensure the value from get_write_protect_state() is being transferred accurately, so that we may read this GPIO value in depthcharge without resampling. The cached value of the "recovery" GPIO is read only on certain boards which have a physical recovery switch. Correct some of the values sent to boards which presumably never read the previously incorrect value. Most of these inaccuracies are from non-inverted values on ACTIVE_LOW GPIOs. BUG=b:124141368, b:124192753, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11google/kukui: Use internal CR50_IRQ pull-upYou-Cheng Syu
For Kukui CR50_IRQ pin, we're going to replace external pull-up with internal pull-up. This change won't break older boards, so we can just always do that when setting up GPIOs. BUG=b:124821269 BRANCH=none TEST=Waveform looks correct. Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-11mb/google/octopus: Disable WLAN prior the entry of S5Kane Chen
ODM reported issues that some systems can't be shutdown to S5 very occasionally. ODM found issue is gone if they remove the WLAN card. So, this change to disable WLAN before system enters S5. This change is validated by ODM and it does help issue. BUG=b:129377927 Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriateElyes HAOUAS
Change-Id: Idcdbbfa883c906db1ebb8d9bc7c9e277e7c0c949 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-10mb/ocp/monolake: Add board.fmdAndrea Barberio
Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7 Signed-off-by: Andrea Barberio <barberio@fb.com> Signed-off-by: David Hendricks <dhendrix@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-09nb/intel/sandybridge: Set uninitialized run lengthJacob Garber
If the entire array is zero, then the length of the longest zero run is the length of the array itself. Found-by: Coverity Scan, CID 1229715 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Id23292087b14182448d70117915fb044e9c579f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-09google/kukui: Configure AP_IN_SLEEP_L correctlyYou-Cheng Syu
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM (a power management component of MT8183) can control it. BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0. Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09mb/google/hatch: Support 16MiB fmapPhilip Chen
Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-09arch/x86/smbios: Reference type 7Patrick Rudolph
Fill in the handle to cache entries of type 7 in the type 4 structure. Tested on Intel Sandy Bridge (Lenovo T520). All 3 caches are referenced. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/smbios: Add type 7Patrick Rudolph
The SMBIOS spec requires type 7 to be present. Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the "Deterministic Cache Parameters" as available on Intel and AMD. As CPUID only provides partial information on caches, some fields are set to unknown. The following fields are supported: * Cache Level * Cache Size * Cache Type * Cache Ways of Associativity Tested on Intel Sandy Bridge (Lenovo T520). All 4 caches are displayed in dmidecode and show the correct information. Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/cpu: Add functions to determine CPU vendorPatrick Rudolph
Add two functions to determine if CPU is made by a specific vendor. Use Kconfig symbols to allow link time optimizations. Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-09mb/google/hatch: Add ACPI support for BT reset functionalityTim Wawrzynczak
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree, on both USB2 port 5 and 10. BUG=b:123293169 BRANCH=none TEST=compiles, verified kernel is able to find the reset-gpio Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09src: Fix remaining #include <timer.h>Nico Huber
Follow-up to add76f91d5 (src: Use #include <timer.h> when appropriate). Change-Id: I7813daa0b73039ec76d33a16ce3ae0ce6cc7f2cc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-08mb/facebook/watson: Make turbo mode configurable (disabled by default)David Hendricks
Change-Id: Ief1eaab960c8fdab5bd5041b1a4f0c6ba1dd833f Signed-off-by: David Hendricks <dhendrix@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32222 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()Nico Huber
We decided to not care about compile-time errors. So drop the comment, the code was updated already. Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-08commonlib/cbfs: Check for presence of CONFIG() macroNico Huber
Check for CONFIG not IS_ENABLED, as we use the former now. Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08soc/amd/stoney: Don't use IS_ENABLED() for a constantNico Huber
IS_ENABLED() was supposed for Kconfig options. Change-Id: Ia40d64856cd89586133e54ff6e02c35d6b647059 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32225 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber
Another run of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I3243197ab852a3fbc3eb2e2e782966a350b78af2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08nb/intel/pineview: Correct lsbpos(0) and msbpos(0)Jacob Garber
lsbpos and msbpos have incorrect behaviour when given 0. lsbpos(0) returns 8, and msbpos(0) hangs. The latter is because the check i >= 0 is always true for an unsigned integer, causing it to loop indefinitely (this was flagged by Coverity). 0 doesn't have a lsb or msb position, so we change both functions to return -1 in this case to indicate an error. The code already guards against calling these functions with 0, but we make this more explicit to prevent errors in the future. Found-by: Coverity Scan, CID 1347356, 1347386 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/32054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08soc/intel/baytrail: Correct array bounds checkJacob Garber
If `gms == ARRAY_SIZE(gms_size_map)`, then we will have an out of bounds read. Fix the check to exclude this case. This was partially fixed in 04f68c1 (baytrail: fix range check). Found-by: Coverity Scan, CID 1229677 (OVERRUN) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08nb/amd/pi, mb/amd/bettong: Fix null pointer checksJacob Garber
The dev pointers were being dereferenced before the null check. Move the checks so they are done earlier. Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-08soc/skl: Update SkipExtGfxScan in UPD from devtreeMaxim Polyakov
The SkipExtGfxScan option is defined in the device tree, but doesn`t update the value in the UPD. It uses the default value - 0. This means that the FSP will scan all external graphics devices, in spite of the configuration in devicetree.cb for a specific board. Patch updates SkipExtGfxScan options in UPD from devicetree.cb. This change affects all boards with skl/kbl processor. Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-08siemens/mc_apl5: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMIMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 Reviewed-on: https://review.coreboot.org/c/coreboot/+/30753 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08{src,util}: Correct typo in comment and debug stringFrans Hendriks
Correct typo in comment and debug string. BUG=N/A TEST=build Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29321 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08mb/mainboard/google/sarien/variants: Set correct tcc_offset valueSumeet Pawnikar
Set new tcc_offset value to 10 degree C. This configures the Thermal Control Circuit (TCC) activation value to 90 degree C. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action when CPU temperature goes above 90 degree C. Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-08mb/google/sarien: Add support for melfas touch panelEric Lai
Add a support melfas touch panel with i2c address:0x34. BUG=b:122019253 TEST=tested with new melfas touch panel and worked Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I27f5c47517d093c819cbbbcdafd85d74145887e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32169 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08src/soc/intel/cannonlake: Remove ITSS IPC restoreAamir Bohra
Remove ITSS IPC restore for cannonlake, as it does not take effect since the ITSS PCR registers are locked post FSP-S. Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-07vc/amd/agesa/f14: Add missing break statementJacob Garber
We do not want to ASSERT(FALSE). Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-07sb/intel/{common,i82801dx}: Improve TCO debug codeJacob Garber
Report unhandled TCO bits (previously dead code). This finishes the work done in 3e3b858 (sb/intel/ibexpeak: Update debug code to match other chips). Found-by: Coverity Scan, CID 1229598 (DEADCODE) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32179 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-07device/pci: Rewrite PCI MMCONF with symbol referenceKyösti Mälkki
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-06mb/amd/bettong/mainboard: Drop unused include <agesawrapper.h>Elyes HAOUAS
Change-Id: I020c1b9558f6aec47b048fa575c64c619b8c592a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32013 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06mb/asrock/h110m: Add PEG Gen3 supportMaxim Polyakov
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image. Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16). GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported. Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload. Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06soc/intel/skylake: Set FSP options for PEG portMaxim Polyakov
FSP options list (for each PEG port): - PegXEnable, - PegXMaxLinkWidth, - PegXMaxLinkSpeed, - PegXPowerDownUnusedLanes, - PegXGen3EqPh2Enable, - PegXGen3EqPh3Method. Add PegMaxLinkWidth to chip.h. This option overrides the number of active lines from the devicetree.cb for each enabled PEG port (for example for boards that use x4 instead of x16 lines in PEG0). If the PegMaxLinkWidth is not defined, the port uses the maximum possible number of lines. To enable or disable the corresponding PEG root port you need to add to the devicetree.cb: device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1 If PEG port is not defined in the devicetree, it will be disabled in FSP. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32045 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06mb/asrock/h110m: Set PEG as primary GFX deviceMaxim Polyakov
If an external graphics card is inserted in the PEG, it will be used as the primary display device (as in the AMI BIOS) Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-20 22:19:49 +0000