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2015-04-18broadwell: add ROM stage pre console init call backWenkai Du
Serial port on ITE 8772 SuperIO must be initialized before console_init is called. So the pre console init callback is added to let mainboard code do proper initialization. Change-Id: Iaa3e4b9c6e7ce77a7b9a6b9ecedd8ea54f3141dc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 71ee2fd470e19fa4854f895678445b05c17761c1 Original-Change-Id: I594e6e4a72f65744deca5cad666eb3b227adeb24 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227933 Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-18kconfig: automatically include mainboardsStefan Reinauer
This change switches all mainboard vendors and mainboards to be autoincluded by Kconfig, rather than having to be mentioned explicitly. This means, vendor and mainboard directories are becoming more "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree mainboards / components to be built with a given coreboot version (given that the API did not change) Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a Reviewed-on: http://review.coreboot.org/9295 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-17cygnus: enable mmuDaisuke Nojiri
this is not only for speed but also preventing the cpu from crashing. the cpu is not happy when cache is cleaned without mmu turned on. BUG=chrome-os-partner:36691 BRANCH=broadcom-firmware TEST=boot purin to romstage. Change-Id: I2445dcc2729798c4fc56fa191cbc8471ef708d08 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e35c925b75213e1d35bf191f22c39aaf1726eeb Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Icaf8c506df258edb99413949e6e3089a2b1a91af Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199388 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/251306 Reviewed-on: http://review.coreboot.org/9768 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17cygnus: configure memlayoutDaisuke Nojiri
we also pick no RETURN_FROM_VERSTAGE. BUG=none BRANCH=broadcom-firmware TEST=booted b0 board Change-Id: Iddd95f233a614187ae6b26f351a289c23f25742f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 243598925333982b40297adad878c461990d7d70 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I6ab96628cecb84e061777cc85d6d572823f6d63c Original-Reviewed-on: https://chromium-review.googlesource.com/251303 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9767 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17cygnus: add timer functionsDaisuke Nojiri
this implements udelay. BUG=chrome-os-partner:36011 BRANCH=broadcom-firmware TEST=measured 10 sec of delay by stopwatch Change-Id: I833b71fac98a871bff71478221a55e1ca15c13df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 137456e63931052f80247b72f98f958afdba8a27 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ib5e33a19421eae900800fce94e9fd51bc2c665c4 Original-Reviewed-on: https://chromium-review.googlesource.com/251302 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9766 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17urara: Define UART used for serial consoleDavid Hendricks
BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara with follow-up patches Change-Id: I0ed55f372e095f6b63a47734c4d223a575f63904 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a013de7daa7bf9d8a5f59e292c2a01401568d738 Original-Change-Id: I8ddf9e65a8ac3d4b09032a741b725c78251f14c9 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243212 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9778 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-17pistachio: Move console UART to a Kconfig variableDavid Hendricks
This allows us to define the serial console UART on a per-board basis. BUG=chrome-os-partner:31438 BRANCH=none TEST=built and booted on urara w/ follow-up patches Change-Id: Idbb0d39bf8855df4312f7499c60b8b92826fdd07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed4cfdd5ed6ccbf87a50f56d3e07f2f1a9d49464 Original-Change-Id: I3faeb92f026062cded390603a610e5b8f7c9bc12 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243211 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: http://review.coreboot.org/9777 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-17Fix non-x86 __PRE_RAM__ assertions and add FATAL_ASSERTS Kconfig optionJulius Werner
This patch fixes a bug that caused non-x86 boards to use the poor man's assert() version with a lot more instructions per invocation and hexadecimal line numbers in __PRE_RAM__ environments. This was really just an oversight in the ARM port... even x86 uses a proper printk() in most cases (those with CAR) and there's no reason not to do so on the generally even more flexible SRAM-based architectures. Additionally, it adds a new Kconfig option to make failed assertions and BUG() calls halt again. This seems to have been the original intention, but was commented out once out of fear that this might prevent production systems from booting. It is still a useful debugging feature though (since otherwise assertions can easily just scroll past and get overlooked), so the user should be able to decide the this based on his needs. (Also changed error messages for both to include the word "ERROR", since grepping for that is the most sophisticated way we currently have to detect firmware problems. Some automated Chromium OS suspend tests check for that.) BRANCH=veyron BUG=None TEST=Booted Jerry. Compared binary sizes before and after, new version's bootblock is some ~600 bytes smaller. Change-Id: I894da18d77e12bf104e443322e2d58e60564e4b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6a5343124719c18a1c969477e3d18bda13c0bf26 Original-Change-Id: I0268cfd67d8c894406b18bb3759a577944bcffb1 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250661 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17flash: use two bytes of device ID to identify stmicro chipsDaisuke Nojiri
stmicro flash chips use 2 bytes as a device id: upper byte for memory type and lower byte for capacity. with this change, we will use all 2 bytes to identify a chip. BUG=none BRANCH=broadcom-firmware TEST=booted purin and verified n25q256a was identified. Change-Id: I8f382eddc4fa70d3deceb4f9d2e82026a7025629 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f70a1d4b7e1142afec9ce097c4a21b6225f66e Original-Change-Id: Id3378a77318fabb74ddb30f1a9549010636872ba Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199387 Original-Reviewed-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/251305 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17storm: Add STM flash supportVadim Bendebury
Compile in support for the STM flash devices. BRANCH=storm BUG=chrome-os-partner:33489 TEST=verified that both spansion and stm flash devices boot as expected. Change-Id: Ib616b2b52d29b20b4447c92115181a92c524ac39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34c0147b45551e9161e3f0e342a753907f27f9ae Original-Change-Id: I922afb91cc3ac5bf459d9746817d7677986b93cd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248993 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17qualcomm/ipq806x: add spi_crop_chunk()Patrick Georgi
That function requirement was added upstream but not in Chromium, so add an implementation. Change-Id: Ie384b315adb205586defa730b843c7c8e96f77fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9776 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17spi: allow inclusion of Micronix and STM drivers in bootblockVadim Bendebury
Bootblock does not allow using malloc, use statically allocated chip structures instead. BRANCH=storm BUG=chrome-os-partner:33489 TEST=both drivers compile when configured in, also booted whirlwind with an STM compatible SPI NOR flash. Change-Id: I154c33ce5fc278d594205d8b8e62a56edb4e177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eedbb959a595e0898e7a1dd551fc7c517a02f370 Original-Change-Id: I29b37107ac1d58a293f531f59ee76b3d8c4b3e7c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17armv7: set CBFS header to zeroVadim Bendebury
This is necessary to make sure that bootblock uses the default CBFS header (as it ought to) when multiple CBFS images support is enabled. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=with the rest of the patches applied storm boots all the way inot the Linux prompt Change-Id: I5e029d95c5cb085794c7bf5f44513b2144661e38 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 75b2c2ef6c8287db7c3e5879cacfd5dcba4391ac Original-Change-Id: I5c352921b4c9b6a3294f4658d174e0842d2ee365 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17pistachio: add DDR2 initialization codeIonela Voinescu
This is the intialization code specific to the Winbond W972GG6JB-25 part using Synopsys DDR uMCTL and DDR Phy. This is DDR2 initialization code only (currently present on the bring up board). DDR3 initialization code will follow for boards having DDR3 memory. The programming procedure that is executed at power up to bring up the uMCTL, PHY and memories into a state where reads and writes to the memory can be performed is the following: 1. uPCTL (Universal DDR protocol controller) initialization The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH needed for driving the memory power-up sequence are programmed as a function of the internal timers clock frequency. Organization (memory chip specific) values are set (column/bank/row address width and number of ranks), together with other static values (latency, timing, power up configuration). All these values are static, provided by the datasheet, being determined by the memory type, size and frequency. 2. PHY initialization The PHY is programmed with datasheet provided values, specifying the initialization values for it to send to the external memory (timing parameters). Also, delay lines (DLL) and strength of drive pads are calibrated (based on external conditions: temperature, voltage, noise) and locked. After that, the PHY goes through a trainig process (also dependent on the current conditions at boot time) to establish precise timing configuration between the DDR clock and DQS (data strobe) and between DQS and DQ (data). 3. Memory power up 4. Switch from configuration state to access state. BUG=chrome-os-partner:31438, chrome-os-partner:37087 TEST=tested on Pistachio bring up board -> DDR initialized properly and ramstage executed correctly DDR2 is also tested during chip sort. Corner cases (performace of DDR in different conditions) will be tested after the chip reaches a stable state. BRANCH=none Change-Id: I0093dc175d064aad03052d5281679b008c1bf012 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d0bacea0fd5bd3b12008b47e80de8398f447785 Original-Change-Id: I8437db6c84d77c4c51a3ee2b09cd3d14913c0d16 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241424 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9769 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17ryu: Add support for EVT board with ID BASE3(1,1)Furquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Ic5c2dafd87641879074f98d023de0379c6e2bfba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ba476b8a436303603d7205d19f66f06c63118cd Original-Change-Id: I6a1404ff23d62100739919e8f569da2041038f01 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/252352 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-17armv7: work around hang in bootblock startup codeDaisuke Nojiri
broadcom cygnus hangs if we clean caches by dcache_clean_invalidate_all at bootblock entry point. this change makes startup code call dcache_invalidate_all instead. other boards theoretically should not be affected as long as maskrom does not hand off execution to bootblock with dirty cache. BUG=chrome-os-partner:36648,chrome-os-partner:36691 BRANCH=broadcom-firmware TEST=boot cygnus b0 board, messages were printed on console: coreboot-688aae9-dirty bootblock Mon Feb 9 13:21:02 PST 2015 starting... Exception handlers installed. Change-Id: I05777ca525c97bb3d7cbb5ea7e872a602dcd5a19 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59de5328df9d0502a3b3f7c624d3e86e038de50e Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I9b8850846b941e7e62712e90cc28ad14a68da393 Original-Reviewed-on: https://chromium-review.googlesource.com/251304 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17storm: handle dual purpose recovery buttonVadim Bendebury
Storm devices' recovery button is overloaded. Pressing it when the system is running is supposed to reset the device. To trigger recovery mode the button must be held pressed for at least 5 seconds after reset. Currently interpreting the recovery button state is the responsibility of the board (vboot gets a consolidated state, which is a combination of several conditions), so the simplest way to implement this feature is to make the board follow the recovery button state. In case the button is not pressed when it is first sampled, its state is saved immediately and no recovery request is reported. In case the button is pressed when it is first sampled, the board code keeps polling it up to 5 seconds and acts accordingly. BRANCH=storm BUG=chrome-os-partner:36059 TEST=tried starting a whirlwind with recovery button pressed for various durations, it entered recovery mode when the button was pressed longer than 5 seconds. Change-Id: Icb3250be7c2a76089c070acd68cb521d1399e245 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 45e7265bc760944f93dd98903d39d2b30aa96365 Original-Change-Id: Iab3609ebce3a74e3d0270775b83f3cf03a8837ca Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/251711 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17ryu: add support for p4 boardsDavid Riley
BUG=none BRANCH=none TEST=P4 board boots and selects correct dts file Change-Id: Icdfdef9b82bd53413e45713f9ceef2e0c2be16a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0674037b1f00845ffcd129cb54571f185b42af40 Original-Change-Id: If14e2586c4ef5b44af1754b3f06126b79473798b Original-Signed-off-by: David Riley <davidriley@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250634 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17ipq806x: extend GSBI driver to support i2c on any GSBI blockSourabh Banerjee
The GSBI driver is extended to be able to program the CTRL reg for any given GSBI block. The NS and MD registers programming is made more readable by programming the M, N, D and other bits of the registers individually. Defined configure structs for each QUP block to be able to track the init status for each qup. Configured GPIO8 and GPIO9 for I2C fuction. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:36722 TEST=Booted up storm P0.2, verified that the TPM on GSBI1 still works. Change-Id: I17906beedef5c80267cf114892080b121902210a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07bc79211770decc1070c3a88874a4e452b8f5bc Original-Change-Id: I841d0d419f7339f5e5cb3385da98786eb18252ad Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/250763 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Trybot-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9759 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17ipq806x: add LPASS clock control driverVadim Bendebury
Add a clock control driver to initialize the clock tree inside the low-power audio subsystem. Depthcharge builds up on this to enable audio function on storm. The clock is hardcoded for 48KHz frame rate, two 16 bit channels. BRANCH=storm BUG=chrome-os-partner:35247 TEST=with depthcharge patches applied and Using depthcharge CLI audio test program verified that the target generates sensible sounds audio 100 100 audio 1000 5000 Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760 Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f Original-Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248830 Original-Reviewed-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: http://review.coreboot.org/9758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: Add software I2C supportJulius Werner
This patch adds the necessary platform glue to allow the use of software-driven I2C bit banging on the RK3288. This is just a debugging feature that can be used to reproduce certain I2C failure cases. Also fix Makefile verstage linking for the feature and add some new rk3288 IOMUX macros as needed. BRANCH=None BUG=None TEST=Added "CONFIG_SOFTWARE_I2C=y" to configs/config.veyron_jerry, wrapped Jerry's bootblock and verstage in software_i2c_attach/detach() calls, confirmed that both PMIC and TPM could be driven correctly with software I2C driver. Tried out different combinations of software_i2c_wedge_ack() and software_i2c_wedge_read() on the PMIC and observed transfer results with the hardware controller after reboot... the worst that would happen is that the first register read-modify-write (DCDC_ILMAX) would fail to read, but all later transfers would be fine. Since that register is written twice (due to current BUCK1 ramp implementation) and is not terribily important anyway, I think we don't need to worry about wedging problems. Change-Id: Iba801ee61d30fb1fd3aef8300612c67fa50c441b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24dfca9bab38a20c40ef0c2dd4c775b8d8f47487 Original-Change-Id: I96777300a57c85471bad20e23a455551e9970222 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247890 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17ipq806x: Add support for mmu in bootblock.Deepa Dinamani
move mmu setup from RAM stage to boot block Enabling mmu earlier, helps speed up the boot time. BRANCH=storm BUG=chrome-os-partner:35024 TEST=Verified the mmu table dump matches the programmed values. Change-Id: I8f581538d5dfd0d78538c9fe50f689d54b740685 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb799a6d61f9c2f478434a71584d0edb94af4b59 Original-Change-Id: I110497875002a88add7eb4312a70c0de8c28bc4f Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/247120 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Trevor Bourget <tbourget@codeaurora.org> Reviewed-on: http://review.coreboot.org/9756 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron_{brain,danger,rialto}: Enable eventloggingDavid Hendricks
This brings brain, danger, and rialto up to parity with other veyron platforms as far as eventlog functionality is concerned. BUG=chrome-os-partner:34436 BRANCH=none TEST="mosys eventlog list" shows events (tested on Brain) Change-Id: I186c5d18e5351c0eaf08ffecfd87506283c44b19 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1764bc53147718031231a6d125a4a1a96c4c6a8f Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ief09299965f6f21bc5a40cef31cde61344025c2a Original-Reviewed-on: https://chromium-review.googlesource.com/239979 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9755 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron_{brain,danger,rialto}: Use common watchdog rebootDavid Hendricks
This applies a previous patch ("chromeos: Provide common watchdog reboot support") to some veyron platforms that were missing it. BUG=none BRANCH=none TEST=built and booted on Brain Change-Id: I3eb431a57367b8f885844e4353a78f77515f5195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b0c87dd4217917a35817c719efe43dd4ec442df0 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I2861939655a995d309847f64cecd974a740fae37 Original-Reviewed-on: https://chromium-review.googlesource.com/245633 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9754 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: move reboot_from_watchdog() before rk808 settinghuang lin
we will use dvs to adjust the voltage in kernel, if device reset by watchdog in kernel, the dvs gpio may not reset, and we use the i2c to adjust rk808 voltage in coreboot, so it may failure. so we move the reboot_from_watchdog() before the rk808 setting. BUG=None TEST=Boot from speedy BRANCH=None Change-Id: I809c63153d49680d9c84462aafd7bae09106fa6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76efb4b0196eecc84664a4c5dce2221152a39c0a Original-Change-Id: I92b5c6413bbffe30566178de89df1f9683790982 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/244289 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17purin: add purin under mainboardDaisuke Nojiri
this change covers bootblock and romstage. BUG=none BRANCH=tot TEST=ran emerge-purin coreboot Change-Id: Ifffb2e93189e8e85338de469432f3296e3e71791 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd479583404958f72461e9c1639f0288a00f228e Original-Change-Id: Iaee4a8c457e42386a4100a8121144b8cf5f21e8c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242853 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17broadcom/cygnus: add new SoC driverDaisuke Nojiri
This commit covers bootblock and romstage. BUG=none BRANCH=tot TEST=ran emerge-purin coreboot Change-Id: I88e2dffb9e46ba5b066190e844a6a7302adcfdc7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3af6343a74263f086fe82c600559e8204e7dec0 Original-Change-Id: I447ed5f6ed181cfc9d5521b8c57e5fe0036a3f71 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242854 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9750 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17chromeos: Provide common watchdog reboot supportJulius Werner
Many ChromeOS devices use a GPIO to reset the system, in order to guarantee that the TPM cannot be reset without also resetting the CPU. Often chipset/SoC hardware watchdogs trigger some kind of built-in CPU reset, bypassing this GPIO and thus leaving the TPM locked. These ChromeOS devices need to detect that condition in their bootblock and trigger a second (proper) reboot. This patch adds some code to generalize this previously mainboard-specific functionality and uses it on Veyron boards. It also provides some code to add the proper eventlog entry for a watchdog reset. Since the second reboot has to happen before firmware verification and the eventlog is usually only initialized afterwards, we provide the functionality to place a tombstone in a memlayout-defined location (which could be SRAM or some MMIO register that is preserved across reboots). [pg: Integrates 'mips: Temporarily work around build error caused by <arch/io.h> mismatch] BRANCH=veyron BUG=chrome-os-partner:35705 TEST=Run 'mem w 0xff800000 0x9' on a Jerry, watch how a "Hardware watchdog reset" event appears in the eventlog after the reboot. Change-Id: I0a33820b236c9328b2f9b20905b69cb934326f2a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fffc484bb89f5129d62739dcb44d08d7f5b30b33 Original-Change-Id: I7ee1d02676e9159794d29e033d71c09fdf4620fd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242404 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Id: c919c72ddc9d2e1e18858c0bf49c0ce79f2bc506 Original-Change-Id: I509c842d3393bd810e89ebdf0dc745275c120c1d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242504 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9749 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron_*: Enable eventloggingDavid Hendricks
BUG=chrome-os-partner:34436 BRANCH=none TEST=Built and booted on pinky w/ depthcharge fmap patch, used mosys to verify that eventlog entries get populated: entry="0" timestamp="2015-01-06 13:45:33" type="Log area cleared" bytes="4096" entry="1" timestamp="2015-01-06 13:45:33" type="System boot" count="0" entry="2" timestamp="2015-01-06 13:45:33" type="Chrome OS Developer Mode" Change-Id: I74ba8b271328453c8b91f11e7858754a80806c31 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 197010f057f4835a30ed2e71f47ca51fc181afe4 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I19cb884be5c3e00975599e96e0223e33d32e7c0d Original-Reviewed-on: https://chromium-review.googlesource.com/238830 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9644 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17chromeos: Move memlayout.h/symbols.h into common directoryJulius Werner
Turns out there are uses for memlayout regions not specific to vboot2. Rather than add yet another set of headers for a single region, let's make the vboot2 one common for chromeos. BRANCH=veyron BUG=chrome-os-partner:35705 TEST=Booted Jerry, compiled Blaze, Cosmos, Ryu and Storm. Change-Id: I228e0ffce1ccc792e7f5f5be6facaaca2650d818 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c6d7aab9f4e6d0cfa12aa0478288e54ec3096d9b Original-Change-Id: I1dd7d9c4b6ab24de695d42a38913b6d9b952d49b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242630 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17storm: define location for storing CBFS header valueVadim Bendebury
The 4 byte offset value will be stored in SRAM and shared between different coreboot stages. BRANCH=storm BUG=chrome-os-partner:3416, chromium:445938 TEST=with the rest of the patches in, storm successfully boots into Linux login prompt Change-Id: Id8df75b0c679e274532660d55410291e59f3b520 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f2f7cf6263f4c2db70b1c87ec67f6b0308059b3 Original-Change-Id: I1ebfada93e222992300cd695d04669988206d4b1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17cbfs: look for CBFS header in a predefined placeVadim Bendebury
This patch introduces a new option (CONFIG_MULTIPLE_CBFS_INSTANCES) to allow multiple CBFS instances in the bootrom. When the new option is enabled, the code running on the target controls which CBFS instance is used. Since all other then header CBFS structures use relative addressing, the only value which needs explicit setting is the offset of the CBFS header in the bootrom. This patch adds a facility to set the CBFS header offset. The offset value of zero means default. i.e. the CBFS initialization code still discovers the offset through the value saved at the top of the ROM. BRANCH=storm BUG=chrome-os-partner:34161, chromium:445938 TEST=with the rest patches in, storm target successfully boots from RW section A. Change-Id: Id8333c9373e61597f0c653c727dcee4ef6a58cd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e57a3a15bba7cdcca4a5d684ed78f8ac6dbbc95e Original-Change-Id: I4c026389ec4fbaa19bd11b2160202282d2f9283c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237569 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9747 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17pistachio: report UART register widthVadim Bendebury
Pistachio UART closely matches 8250, the only difference is that its register file is mapped to a 32 bit bus. Provide a function to report register with so that the Coreboot table entry gets correct value. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087 Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240028 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-17blaze: add new Hynix 2GB BCTNeil Chen
- Hynix H5TC4G63CFR-PBA, ramcode = 5 BUG=chrome-os-partner:34695 TEST=emerged coreboot, booted successfully into kernel. Change-Id: I53f9ebd9c38c645d1eb8b685d39e8beb55bd3c6a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee6fdcc28402fe324d08b713498488d863d1d30f Original-Change-Id: I829d4e1f992eadd445c313729eb4bca5ce602f53 Original-Reviewed-on: https://chromium-review.googlesource.com/245947 Original-Reviewed-by: Neil Chen <neilc%nvidia.com@gtempaccount.com> Original-Tested-by: Neil Chen <neilc%nvidia.com@gtempaccount.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Neil Chen <neilc%nvidia.com@gtempaccount.com> Reviewed-on: http://review.coreboot.org/9736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17exynos: return correct value when init_default_cbfs_media failsDaisuke Nojiri
BUG=none BRANCH=ToT TEST=Built daisy. Change-Id: I64033f8e7beb247b2b8bd66e58de6c5e263ee634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ff51e887a07a0f2426e5111df683ce2a9d4097d Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id6e006be1db08933dc97b5e797a85f3cbf9f6486 Original-Reviewed-on: https://chromium-review.googlesource.com/232513 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9735 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: detect sdram size at runtimehuang lin
we use Kconfig define sdram size before, but there may use different sdram size in the same overlay, so we must detect sdram size at runtime now. If we use 4G byte sdram, we can use[0x00000000:0xff000000], since the [0xff000000:0xffffffff] is the register space. BUG=chrome-os-partner:35521 TEST=Boot from mighty BRANCH=None Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898 Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243139 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron: move setup_chromeos_gpios() prototype to board.hJulius Werner
I always had that TODO comment in there but I had already forgotten what I even meant by it. It's really just a simple cleanup... this function is (currently) veyron-specific and doesn't belong in common code. BRANCH=veyron BUG=None TEST=Booted Jerry. Change-Id: Iccd6130c90e67b8ee905e188857c99deda966f14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d188398704575ad2fedc2a715e609521da2332b0 Original-Change-Id: I6ce701a15a6542a615d3d81f70aa71662567d4fa Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241190 Reviewed-on: http://review.coreboot.org/9733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: Handle framebuffer through memlayout, not the resource systemJulius Werner
We've traditionally tucked the framebuffer at the end of memory (above CBMEM) on ARM and declared it reserved through coreboot's resource allocator. This causes depthcharge to mark this area as reserved in the kernel's device tree, which may be necessary to avoid display corruption on handoff but also wastes space that the OS could use instead. Since rk3288 boards now have proper display shutdown code in depthcharge, keeping the framebuffer memory reserved across the handoff (and thus throughout the lifetime of the system) should no longer be necessary. For now let's just switch the rk3288 implementation to define it through memlayout instead, which is not communicated through the coreboot tables and will get treated as normal memory by depthcharge. Note that this causes it to get wiped in developer/recovery mode, which should not be a problem because that is done in response to VbInit() (long before any images are drawn) and 0 is the default value for a corebootfb anyway (a black pixel). Eventually, we might want to think about adding more memory types to coreboot's resource system (e.g. "reserved until kernel handoff", or something specifically for the frame buffer) to model this situation better, and maybe merge it with memlayout somehow. CQ-DEPEND=CL:239470 BRANCH=veyron BUG=chrome-os-partner:34713 TEST=Booted Jerry, noticed that 'free' now displays 0x7f000 more bytes than before (curiously not 0x80000 bytes, I guess there's some alignment waste in the kernel somewhere). Made sure the memory map output from coreboot looks as expected, there's no visible display corruption in developer/recovery mode and the 'cbmem' utility still works. Change-Id: I12b7bfc1b7525f5a08cb7c64f0ff1b174df252d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10afdba54dd5d680acec9cb3fe5b9234e33ca5a2 Original-Change-Id: I1950407d3b734e2845ef31bcef7bc59b96c2ea03 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240819 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9732 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17arch/mips: Fix bug when performing cache operationsIonela Voinescu
Each type of cache might have different cache line size. Call the proper get_<*>cache_line function for each cache type. Fixes problem with get_L2cache_line which previously targeted L3 cache line in the config register, instead of L2 cache. TODO: add support for tertiary caches and have cache operations be called per CPU, not per architecture. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; worked as expected; BRANCH=none Change-Id: I7de946cbd6bac716e99fe07cb0deb5aa76c84171 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 62e2803c6f2a3ad02dc88f50a4ae2ea00487e3f4 Original-Change-Id: I03071f24aacac1805cfd89e4f44b14ed1c1e984e Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241853 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17spi: Add function to read flash status registerDuncan Laurie
Add a function that allows reading of the status register from the SPI chip. This can be used to determine whether write protection is enabled on the chip. BUG=chrome-os-partner:35209 BRANCH=haswell TEST=build and boot on peppy Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240702 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c58f17689162b291a7cdb57649a237de21b73545) Change-Id: Ib7fead2cc4ea4339ece322dd18403362c9c79c7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbdf0d72892eef4a742a418a347ecf650c01ea5 Original-Change-Id: I2541b22c51e43f7b7542ee0f48618cf411976a98 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241128 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17drivers/spi: Pass flash parameters from coreboot to payloadDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17Add delay before reading GPIOs in gpio_base2_value()David Hendricks
This adds a 10us delay in between (re-)configuring and reading GPIOs in gpio_base2_value() to give the values stored some time to update. As far as I know this hasn't bitten us since the function was added, but adding a short delay here seems like the right thing to do. BUG=none BRANCH=none TEST=built and booted on Brain Change-Id: I869cf375680435ad87729f93d29a623bdf09dfbc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2484900fc9ceba87220a293de8ef20c3b9b20cfd Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I79616a09d8d2ce4e416ffc94e35798dd25a6250d Original-Reviewed-on: https://chromium-review.googlesource.com/240854 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17urara: add board id information for urara boardIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; works as expected. BRANCH=none Change-Id: If4493fcb37cf649fb0a56d594ac58556da3aa571 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f6764396be1ab17875d9c73624cce48dc6790e6 Original-Change-Id: I925ebd6ea4fc30c1c1d91559f96eaad62d06aba8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239490 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9724 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17as3277: Fix month-off-by-one error for RTC driverJulius Werner
The AS3277 RTC code seems to closely follow the corresponding Linux driver. Unfortunately, while coreboot (and even other parts of Linux, like mktime()) directly follows the standard IBM PC RTC time representation (except for the BCD part), Linux' struct rtc_time decided to use 0-based (instead of 1-based) months instead. This patch removes the faulty month offset that was copied into our driver so that we will generate correct timestamps again. BRANCH=nyan BUG=chrome-os-partner:34108 TEST=firmware_EventLog (pre-release version) gets further than before (and then craps up on unrelated problems with suspend/resume events). Change-Id: Ica221a8bcfd7c1c6cd7ba382d760b586d511e3a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b55c3f5bbecc776a71338256b910aecccac1e04 Original-Change-Id: I163fa4778ec534cd9e6f92a6b6dc55e9871a6a82 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238122 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17bg4cd: define custom romstage entryDaisuke Nojiri
this change defines a custom romstage entry for bg4cd. the entry code stalls subcores, sets up the stack, and clears the bss before jumping to main. BUG=none BRANCH=tot TEST=built all current boards. booted cosmos p1 Change-Id: Idde43f94555bec7804a16928c58ce673956a39e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a35e12eb29b351cc0baaea24344f00d2ba905f6 Original-Change-Id: I9172e873a43847f3ea82cd1d9fd0841f0db83994 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238022 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17arm: allow custom stage entry codeDaisuke Nojiri
this change defines stage_entry as a weak symbol so that a board can implement custom stage entry code. BUG=none BRANCH=tot TEST=built all current boards. booted cosmos p1. Change-Id: If8f6945ecdc5047558bb6359aa997867e36f33b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 86d5008981d0b01652907baab47a476d784a2ceb Original-Change-Id: Ib43158c4013e6393d86a9aef37cf444a48b9fc79 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238021 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: Add a config variable hack to skip display initDavid Hendricks
The current display init code causes Brain to crash when trying to allocate resources. This just avoids doing display init if a config variable is set. Once code has been implemented to properly setup different types of displays we can get rid of this hack. BUG=none BRANCH=none TEST=built and booted (to depthcharge) on Brain, compiled for pinky with FEATURES=noclean and ensured config variable is 0 Change-Id: I9a7266c6bff5b7a6eb05b2b21fb65797bee392d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 804632ca67eaaf4174ca597d83b8923cb9abd1b7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I04c9e8181c58fa0608fd20776fa8c4798a023474 Original-Reviewed-on: https://chromium-review.googlesource.com/235922 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron: Activate Winbond SPI driverJulius Werner
This patch activates the chip driver for Winbond SPI flash (which, incidentally, looks 99.9% the same as the Gigadevice driver but still requires some extra 500+ bytes of object code... there's definitely room for improvement here). Shuffle around rk3288 memlayout to make a little more room in the bootblock. BRANCH=veyron BUG=chrome-os-partner:34176 TEST=Booted Pinky. Checked bootblock and verstage memsz of final binary and noticed that both only have less than 500 bytes left against their memlayout boundary. The next piece of code we add will cause some serious headaches... Change-Id: I97ea6ac334104e4219e310afc557c164b2ff19d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8769e5a34ad3cd417132646fbb58ff51c29fb640 Original-Change-Id: Id2f1204c30aa28251cf85cb80d7ca44947388dba Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236977 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9719 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15rk3288: support edp HPD functionhuang lin
we use the delay 200ms to meet the edp power timing request before, it waste time, so we use the HPD function to detect the edp panel now. In previous version, the hardware may not support the edp HPD function, so in the code it will spend 200ms to detect hpd single, if it don't get the hpd single, it will contiue the edp initialization process, to compatible all of the hardware version. BUG=chrome-os-partner:35623 TEST=Boot from Mighty, and display normal BRANCH=None Change-Id: I82c6a80e37fa42eef3521e6ebbf190d7e80fcece Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7a5343eb9af12cae9a15284217762a91ae24bac6 Original-Change-Id: I21c0ef6ce4643e90a192d8b86659264895b5fda9 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242792 Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: http://review.coreboot.org/9659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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