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2014-11-11lib/malloc.c: Remove pre-proc guard around includeEdward O'Callaghan
Guards around #includes only hide deeper issues. Change-Id: I0a356360eb3919910a980966213a2c53e99e77eb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7424 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-10AGESA f14: Add "const" modifiersEdward O'Callaghan
Apply commit 283ba78415 to f14 (literally, plus one adaptation). Change-Id: Ieea47470e5852ec8a46596ce23a2d18444618624 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7361 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09sch: Move to implicit length patchingVladimir Serbinenko
Change-Id: I057e7d30fa3c661e83db09e27278ce9f0bec69d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7330 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09car globals: add "used" attributePatrick Georgi
Otherwise clang feels free to optimize away that variable (somewhat) and revive it in a different form inside .bss. They probably have the language lawyery excuse for why that's perfectly legal, so let's play it safe. (relevant URL, sorry ron: http://llvm.org/bugs/show_bug.cgi?id=9520) Change-Id: I603312ceea7207088dd29453cc8fb8f48c31af21 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7357 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09i945: consolidate sb & nb early initsVladimir Serbinenko
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7062 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09i945: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Idc3522807b17e56bdaf8f04b4bd68c6ed9777363 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7110 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09Kconfig: Hide DYNAMIC_CBMEM.Vladimir Serbinenko
Only one setting actually works (exact value depends on board). So no need to show it. Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7359 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09lenovo/wacom: Move to implicit length patchingVladimir Serbinenko
Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7331 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09i82801ix: Move to implicit length patchingVladimir Serbinenko
Change-Id: I4027bc8c017901781ae56c7d3bd751bac50719f2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7329 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09i82801gx: Move to implicit length patchingVladimir Serbinenko
Change-Id: Idba0f33d231084d02392e23026f567c30f77b316 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7328 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09haswell: Move to implicit length patchingVladimir Serbinenko
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7327 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09ibexpeak, bd82x6x: Move to implicit length patchingVladimir Serbinenko
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09Provide ability to integrate with QComm SBLsVadim Bendebury
Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary user provided bootloader. The only bootloader requirements imposed by the SBLs are that it is concatenated with the SBL chunks in the bootprm AND it uses MBN encapsulation (mostly to specify the size and load address). This patch adds configuration options to specify the location of the SBL blobs and to require MBN encapsulation of the bootblock. BRANCH=none BUG=chrome-os-partner:27784 TEST=manual - the below demonstrates added encapsulation, no code run attempts have been made yet: $ FEATURES=noclean emerge-storm coreboot $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999 $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3 0000000 00000005 00000003 00000000 2a010000 0000020 00000be0 00000be0 2a010be0 00000000 0000040 2a010be0 00000000 e32bf0df e59f0030 Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193511 (cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b Reviewed-on: http://review.coreboot.org/7261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09arm: Thumb ALL the things!Julius Werner
This patch switches every last part of Coreboot on ARM over to Thumb mode: libpayload, the internal libgcc, and assorted assembly files. In combination with the respective depthcharge patch, this will switch to Thumb mode right after the entry point of the bootblock and not switch back to ARM until the final assembly stub that jumps to the kernel. The required changes to make this work include some new headers and Makefile flags to handle assembly files (using the unified syntax and the same helper macros as Linux), modifying our custom-written libgcc code for 64-bit division to support Thumb (removing some stale old files that were never really used for clarity), and flipping the general CFLAGS to Thumb (some more cleanup there as well while I'm at it). BUG=None TEST=Snow and Nyan still boot. Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182212 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a) Conflicts: payloads/libpayload/include/arm/arch/asm.h src/arch/arm/Makefile.inc src/arch/arm/armv7/Makefile.inc *** There is an issue with what to do with ramstage-S-ccopts, and *** will need to be covered in additional ARM cleanup patches. Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09build: Add ccopts back into the buildMarc Jones
The ccopts mechanism is needed for passing ARM assembler flags to GCC. There are many gotchas in adding ASFLAGS. As things have moved around, the revert doesn't remove cleanly, so this reverts and cleans up the ccopts. This reverts commit 25b56c3af514faa8a730d56fe14cae4960ac83aa. Change-Id: I44c025535258e6afb05a814123c10c24775a88e8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7352 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-08acpigen: Add new function acpigen_pop_lenVladimir Serbinenko
acpigen_patch_len doesn't really need its argument: length always includes everything from length bytes to current pointer and never bytes before it. Hence just infer all the info implicitly. Argument is wrong in several places through the codebase but ACPI parsing is lax enough to swallow incorrect SSDT. After this function is used throughout the codebase, these issues will be fixed. Change-Id: I9fa536a614c5595146a7a1cd71f2676d8a8d9c2f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7325 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-08fsp_rangeley: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-08ibexpeak: Move to common FADTVladimir Serbinenko
Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7201 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-08bd82x6x: Move to common FADT.Vladimir Serbinenko
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-08device/dram/ddr3.c: Fix sizeof on array func param overflowEdward O'Callaghan
The sizeof on array function parameter will return size of 'u8 *' instead of 'spd_raw_data' (aka 'u8 [256]' leading to an overflow. Found-by: Clang Change-Id: I78e113a640b2953c853eb43bd6874e4694260b1f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7353 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-07mainboard: Trivial - Make AGESA board include consistentEdward O'Callaghan
Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7238 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07drivers/ioapic: DEVICE_NOOP some stub function callbacksEdward O'Callaghan
Just when you thought you found them all.. Reduces loc and makes NOP's explicit. Change-Id: I416e0468b7f2f462c940daae695d67fb409aa4c6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7350 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07drivers/net/ne2k.c: Collect headers and defines to top of fileEdward O'Callaghan
Change-Id: I2ffb0dd9fe400132f6d430f115f962b5f8578efa Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7292 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-07cpu/intel/fsp_model_406dx: Invaild include pathEdward O'Callaghan
Found-by: Clang Change-Id: Iac54755caadc3ffbe8a09d40aed8500c2359e829 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7349 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-06northbridge: DEVICE_NOOP some stub function callbacksEdward O'Callaghan
Reduces loc and makes NOP's explicit. Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7344 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-05mainboard/packardbell/ms2290: Missing romstage headerEdward O'Callaghan
cpu/intel/romstage.h is needed so the the main() has a prototype in freestanding. Change-Id: I5e6afef82a4f63ab42927725adf3881084a1e25c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7235 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-05Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'Edward O'Callaghan
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7196 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05pci_ops.{c,h}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: I7cf7c236f94314d7970b19063d73db788c8267e5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7227 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05soutbridge/*/bootblock: Use pci_dev_t over device_t typedefEdward O'Callaghan
Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7193 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05ARM: Use local versions of libgcc functions instead of linking against libgcc.Gabe Black
The flags used to compile libgcc may make it incompatible with the code it's linked against, and/or the hardware it's going to run on. Rather than try to tease the right libgcc from the compiler, lets just leave it out and use our own implementations of the necessary functions. Most of these implementations were taken from the Linux kernel, except for uldivmod.S which was taken from a CL originally written for U-Boot by Che-Liang Chiou in December of 2010. It was modified to not use the CLZ instruction on machines that don't have it, anything earlier than ARMv5. The top block was taken from an earlier version of the same CL which didn't use CLZ in that spot. The later block was written from scratch. BUG=None TEST=Built and booted into the bootblock on nyan. Ran a series of tests which divided and modded a 64 bit value by various 32 bit values which were powers of 2. Confirmed that this function was used and that the returned value was correct. Printed decimal and hex versions of some values and verified that they equaled each other. Built and booted on pit with serial enabled. BRANCH=None Original-Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/172401 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit be8c7a8f3292a7d7651b7c6dafc9a2c53afbd402) *** This second patch is cherry-picked and squashed again to *** pick up the libgcc changes that were skipped previously. arm: Move libgcc assembly macros to arch/asm.h libgcc/macros.h contains some useful assembly macros that are common in Linux kernel code and facilitate things such as unified ARM/THUMB assembly. This patch moves it to a more general place where it can be used by other code as well. BUG=None TEST=Snow still boots. Original-Change-Id: If68e8930aaafa706c54cf9a156fac826b31bb193 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182178 Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit a780670def94a969829811fa8cf257f12b88f085) *** Additional changes for stage specific builds Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie3e48f34ebf6fbe20c3dd76ecbcbea7844e9466e Reviewed-on: http://review.coreboot.org/7322 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-04i82801gx: Handle whole FADT in southbridge.Vladimir Serbinenko
Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7199 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-04amd/agesa/f16kb: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7302 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
Bring code inline to be consistent with the rest of coreboot. See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase, 'expressions that refer to functions get converted to pointers to those functions' Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7290 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04mainboard/dmp/vortex86ec: Unused variable in romstage.cEdward O'Callaghan
Change-Id: I9cc549b7862ee535928bd06b5fb4bd38bb67a992 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7279 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04superio/ite: Use common dispatch for pnp entry/exit functionsEdward O'Callaghan
We already have these implemented under superio/common, use those instead of this copy-paste syndrom. Change-Id: I7c7737e0b3c284d8b14b36c70681ab2269bb1d4b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7310 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04romstage: Pass .car.data as ignored section while adding romstageFurquan Shaikh
We don't want segment for .car.data section to be considered while elf_to_stage transformation is being done. Thus, use -S option for add-stage. Change-Id: I04868c892e3aa94113189b012d284d52bacea5f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/7305 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-03AMD boards: constify romstage variablesPatrick Georgi
That takes them out of .data Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7313 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-03AGESA f12: Add "const" modifiersPatrick Georgi
Apply commit 283ba78415 to f12 (literally, plus one adaptation). Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7312 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-03Revert "gigabyte/ga-b75m-d3h: Add new Intel mainboard"Vladimir Serbinenko
Breaks abuild and is dependent on WIP, is WIP itself. This reverts commit d7d0c8134854cba72f0c3fe25946b27ce0364b43. Change-Id: I8b589b41632696aa4570abcceab5f3a3b0784649 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7319 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-02intel_wifi: Export the SMBIOS structure required by intel driver.Vladimir Serbinenko
Change-Id: I22984a1bc7ca3be6593143af4fce8d5bfe469837 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7295 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-02gigabyte/ga-b75m-d3h: Add new Intel mainboardDamien Zammit
This is based on LENOVO X230 port. Board boots to linux via SATA. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS 3. USB does not work. SeaBIOS/GRUB2 do not detect devices connected to USB ports 4. Sound needs corrected codec verb settings Change-Id: Ib465a4824ef1a71ab6aa17bd40fc281215c6d44f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7020 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-02intel/bd82x6x: Add new current for native USB portsDamien Zammit
Change-Id: I88ef36b94b961a318d280d8de1b8721fcbeb93b0 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-02amd/agesa/f15: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: I52da16b39293c8aeff150db83b8b1aeaa232c205 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7299 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f12: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ife26fb5eca5164e72b5e55eba90757253765b633 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7300 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-02amd/agesa/f10: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ic1bd19087a4500ba0ca9e312ea351e301ab42518 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7301 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01superio/fintek/f81216h: Implement device supportEdward O'Callaghan
Change-Id: I20a34b569f109dd12af29e9e0cee8f7f6b8ebb80 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7309 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01superio/common/conf_mode.c: Introduce 'new' enter/exit keys for SIO'sEdward O'Callaghan
Super I/O manufactures have found new and innovative ways to enter and exit out of LDN config in PNP config space. Change-Id: Id3f5882664f1b2b18b49f32373430cf4b037ad22 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7308 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
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