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2021-03-03soc/intel/tigerlake: Re-use existing define in CrashLog implementationFrancois Toguo
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS. This fix re-uses an already existing variable in crashLog. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/purism/librem_mini: Implement `die_notify`Angel Pons
Make the SATA LED blink when coreboot dies. GPIO functions aren't compiled in for postcar, so add a check to prevent linker failures. TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and also blinding LED). Re-install RAM (and re-seat RAM a few times), boot to OS, and observe SATA LED operating normally, as expected. Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Backport SMRR locking supportAngel Pons
Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking support) to other client platforms. The SMRR MSRs are core-scoped on Skylake and Ice Lake, at least. Older platforms do not support SMRR locking, but now there's seven copies of the same file in the tree. A follow-up will deduplicate smmrelocate.c files into common CPU code. I cannot test Jasper Lake nor Elkhart Lake, but they should still work. As per documentation I do not have access to, Elkhart Lake seems to support SMRR locking. However, Jasper Lake documentation is unclear. Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR MSRs have the same value on all cores/threads (i7-8565U supports HT). Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-03mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG deviceArthur Heymans
Pineview does not support PEG. Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/intel/d510mo/devicetree.cb: Indent with tabsArthur Heymans
This is a cosmetic change. Make the formatting consistent with the rest of the tree. Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/gigabyte: Add GA-D510UDAngel Pons
Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Native raminit chokes with a DIMM in the second slot, but the first slot works properly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-03lib/cbfs.c: Fix return value of failure to measureArthur Heymans
Returning an error on a failure to measure makes the system not bootable. Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-03mb/google/dedede/var/drawcia: Re-tune override GPIO tableKarthikeyan Ramasubramanian
There is going to be an upcoming board version for Drawlat/man and Drawcia. Hence apply the override GPIO table without pad termination for board versions 6 or 8 alone. BUG=None BRANCH=dedede TEST=Build and boot to OS in Drawcia. Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-03mb/google/guybrush: Add SPDs to build for Guybrush variantMartin Roth
These files were automatically generated by the lpddr4 version of gen_part_id.go. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3797ba6d52248961418000614a4f7885182521a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/guybrush: Add generated LPDDR4x SPDsMartin Roth
These SPDs were generated by the lpddr4 version of gen_spd.go from the global_lp4x_mem_parts.json.txt file. BUG=b:178715165 TEST=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-02google/trogdor: Fix trogdor-rev1 eDP power GPIOJulius Werner
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other special case) or rev2 (works like CoachZ/Homestar), rev1 used the same pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still some people using these, so add in another special case for that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02soc/amd/cezanne: Disable legacy DMA IO portsRaul E Rangel
The legacy DMA is not used by linux. This change frees up those IO ports. When FSP-S runs, it re-enables the legacy DMA IO region, so we need to disable it again. BOOTBLOCK: PMx00: 0xe3060bf3 ROMSTAGE - Before FSP: PMx00: 0xe3060bf3 ROMSTAGE - After FSP: PMx00: 0xe3060bf7 BUG=b:180949454 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/amd/majolica: Enable required devices in devicetreeMathew King
Most devices are now disabled by default in the chipset. Enable the iGPU and two XHCI controllers that are required to boot the board. BUG=b:180528708 TEST=To be tested Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02mb/google/guybrush: Set up FW_CONFIG fieldsMathew King
BUG=b:180523962 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-02mb/google/guybrush: Add eSPI configurationMathew King
BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02soc/amd/cezanne: Fill out pci devices in chipset.cbMathew King
BUG=b:180528708 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-02mb/google/brya: Fix a few mistakes in brya0 overridetreeTim Wawrzynczak
1) Both SAR sensors had a UID of `2`, making them indistinguishable 2) No `device` underneath max98357a `chip` Change-Id: Icf586229532819a7779652cbee73755b036dfbdc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02soc/amd/common/blocks/lpc: Explicitly disable serial IRQRaul E Rangel
The serirq enable bit defaults to true, so if we want it disabled, we need to explicitly disable it. BUG=b:180631748 TEST=Boot majolica and see spurious IRQ 9 gone. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-02mb/lenovo/x200: Fix docking eventsNico Huber
Even though `device` entries are children of `chip` entries in the devicetree source format, the chips in the translated C structures are only hooked up to device nodes. Hence, to configure a chip in a device- or overridetree, it always needs a `device` below it. This should fix docking events for the X200 ThinkPad. Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067 Signed-off-by: Nico Huber <nico.h@gmx.de> Found-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kevin Keijzer Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-02mb/google/guybrush: Add option to toggle GPIO for sign of lifeMathew King
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing. BUG=b:180721202 TEST=builds Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-01soc/intel/skylake: Move `gspi_early_bar_init()` callAngel Pons
For consistency with newer platforms, do this in pch.c instead. Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/cannonlake: Drop unnecessary guardAngel Pons
The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This is to ease factoring out common code across seven Intel platforms. Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/{skl,cnl}: Do not chain-include systemagent.hAngel Pons
Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01skylake,fsp1_1: Delete dead `report_memory_config()` functionAngel Pons
RAM is not yet configured in bootblock. This function was copy-pasted from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in there can be removed as nothing else uses them. Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Extract fsp_params.c out of romstage.cAngel Pons
Done for consistency with newer platforms. Also clean up includes. Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Drop `romstage_pch_init()` functionAngel Pons
It only calls `smbus_common_init()`, so just call that directly. Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/{skl,icl}: Move tco_configure() to bootblockAngel Pons
Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move tco_configure to bootblock) to other platforms. This is for consistency. Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/icelake: Rename `pch_init()` functionAngel Pons
There's two instances of the same function, one for the bootblock and another for romstage. Prefix them with the stage they are executed in. Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Drop unused function prototypesAngel Pons
Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common smbus.hAngel Pons
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definitionAngel Pons
According to document 332691-003EN (SPT-H datasheet volume 2), the hardware defaults to 0x44, which matches what newer platforms use. Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Move soc_acpi_name()Angel Pons
Done for consistency with newer platforms. Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Clean up SD GPIO handlingAngel Pons
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Remove unused macro in cpu.hAngel Pons
Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHzKane Chen
Modify I2C3 setting to follow I2C specification (lower than 400kHz). Original setting: .rise_time_ns = 184 .fall_time_ns = 42 Change to: .rise_time_ns = 110 .fall_time_ns = 34 BUG=b:181091107 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01nb/intel/sandybridge: Clean up `dram_timing` functionAngel Pons
Compute timings first, then display them. Drop unneeded comments, too. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45501 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01sb/intel/bd82x6x: Turn ME PCI register structs into unionsAngel Pons
This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr` wrappers. Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/amd/cezanne: Add PSP whitelist debug unlock supportRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak
DPR register's size field is given in whole MiB, so correct where it is used to ensure the correct size multiple (KiB vs. MiB) is used with it. Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling") Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01acpi: Move PCI functions to separate fileTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/common/gpio: Add gpio_routes_ioapic_irq functionTim Wawrzynczak
This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01sb/intel/lynxpoint/me_9.x.c: Rename to me.cAngel Pons
This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflowAngel Pons
The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide. Clamp any values that would overflow this field. Bits in TC_DTP already get set when the tXP and/or tXPDLL values are large. Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/broadwell: Use ctdp.asl from HaswellAngel Pons
Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's. Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 12:08:06 +0000