summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2014-01-13drivers: Add support for X-Powers AXP209 PMUAlexandru Gagniuc
Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12drivers/spi/eon: Add EN25Q64Vladimir Serbinenko
chip found in X230 if not using hardware sequencing. Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4616 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12X60: Enable WWAN by default.Vladimir Serbinenko
Change-Id: I8e51a8fc03c1d7dbbdc11b121b3ea3ec18f65a5a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4670 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12acpi/ec: Add missing delaysVladimir Serbinenko
Without these delays on fast systems like X230 the port is read before it's updated. Change-Id: I3e01fc348cc5170cec108a05095ba301055ed6b0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4617 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12sandybridge: Use calls rather than asm to call to MRC.Vladimir Serbinenko
Using asm as it's done currently is unsafe because caller-saved registers are not declared as clobbered. Using real call is nicer. regparm((1)) ensures that argument is passed in %eax as expected. Change-Id: I7449182582eaa53d4e473bc834b472edd8ee0d30 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Add backlight control.Vladimir Serbinenko
Change-Id: I773793bf53d91ae787bd0d0ae7bd882243196d56 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Make trackpoint enable a CMOS option.Vladimir Serbinenko
To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Remove trackpoint_enable from device tree.Vladimir Serbinenko
Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: make wlan config a CMOS optionVladimir Serbinenko
To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Allow control of low-battery beep.Vladimir Serbinenko
Change-Id: I2f422e83f2afcf0cc3f3ecbace01a8f4f39e87d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Allow user to disable powermanagement beeps.Vladimir Serbinenko
They're pretty annoying. Change-Id: I44d26dc168927a9cedfd6ecc4c9a51a3a7b362c7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ibexpeak / bd82x6x: Make SATA mode user-visible option.Vladimir Serbinenko
Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ibexpeak: Fix timings for IDE mode.Vladimir Serbinenko
Change-Id: I3c89bb633c32a2c2db349cb4fcbe1ed1c8deb5af Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Implement sticky Fn option.Vladimir Serbinenko
Useful for accessibility. Sticky modifier (sticky Fn) is a behaviour of modifier key when you don't have to hold it pressed to achieve the result. E.g. with normal Fn brightness up is: <Press Fn> <Press Home> <Despress Home> <Depress Fn> With sticky Fn you can do: <Press Fn> <Depress Fn> <Press Home> <Despress Home> Change-Id: I4da5adcea02428d936023891de08684cae77c44e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Add an option to swap ctrl and fn.Vladimir Serbinenko
Tested on my X201 and X230. Change-Id: I3c7ec65681157d15c6e87eea64779a08e03ae5a8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_fileVladimir Serbinenko
Number one reason to use cbfs_get_file was to get file length. With previous patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4674 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-12ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.Vladimir Serbinenko
wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4651 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12arch/x86/acpi/globutil.asl: Make control method `S2BF` serializedPaul Menzel
This changes eliminates a warning from the ASL compiler. Change-Id: I502cca731b6b4cd3e17c57fc191f1eed10a5a1fe Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4093 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-11intel/fsp: Fix microcode includingPatrick Georgi
IS_ENABLED() requires the full define (incl. CONFIG_ prefix) but isn't needed here. Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/4646 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-10Remove sprintfVladimir Serbinenko
Remove sprintf as if you can't easily use snprintf then you probably have buffer overflow. Change-Id: Ic4570e099a52d743aca938a2bfadb95981adc503 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4280 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10Replace all occurences of sprintf with snprintfVladimir Serbinenko
THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10console/vsprintf: Implement snprintfVladimir Serbinenko
snprintf is a safe variant of sprintf. To avoid buffer overflows we shouldn't use sprintf at all. But for now let's start by implementing snprintf in first place. Change-Id: Ic17d94b8cd91b72f66b84b0589a06b8abef5e5c9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4278 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2014-01-09X201: set default USB debug controller to 2.Vladimir Serbinenko
The other port is not easily accessible. Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-09bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurableVladimir Serbinenko
DRAM reset gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-09cpu/allwinner/a10: Import raminit code from ubootAlexandru Gagniuc
The memory initialization code is a work in progress for uboot, so we only import the bits needed to get RAM up and running. Any refactoring is cosmetic, and any functional refactoring should be done in separate patches, and preferably, in coordination with the sunxi team. Since it's not yet determined if we should initialize memory during the bootblock or romstage, we don't add raminit to the build just yet. Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4597 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cpu/allwinner/a10: Add low-level helpers for DRAM clock controlAlexandru Gagniuc
PLL5 is special in that it controls the DRAM clock, and requires a fine-grained low-level control which will be needed by raminit code. This change also brings functionality which will be needed by raminit. Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4593 Tested-by: build bot (Jenkins)
2014-01-09cubieboard: Initialize memory in bootblockAlexandru Gagniuc
Even though the Allwinner A10 is limited to a 24KiB bootblock, the memory initialization takes only about 3KiB and leaves enough room for an MMC or NAND driver, so init the memory early on. The advantage is that we can eliminate complicated logistics of where to cache CBFS and where to load the ramstage in SRAM. Change-Id: Id549552ed509434e831db60deaef28e04d62417f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4630 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cubieboard: Keep AHB clock within specsAlexandru Gagniuc
The CPU was clocked at 384MHz in the bootblock, but the AHB bus has a maximum rated frequency of 250MHz. Its clock needs to be divided to keep it within spec. Overclocking the AHB bus hung the CPU when memory was accessed. Change-Id: I7cb9cdd1f126b3d5b0446fc68af79b54946bc2d3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4629 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cubieboard: Turn on green LED during bootblockAlexandru Gagniuc
Change-Id: I807060bde374e4a42abe306cecf838ab157c9515 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4600 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cpu/allwinner/a10: Add functions for driving GPIO pinsAlexandru Gagniuc
Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4599 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cpu/allwinner/a10: Add definitions for in/output GPIO functionsAlexandru Gagniuc
Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4598 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cpu/allwinner/a10: Add function for reading chip revisionAlexandru Gagniuc
Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4596 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cpu/allwinner/a10: Implement udelay using timer 0Alexandru Gagniuc
Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4595 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cpu/allwinner/a10: Add definition for gating GPIO S clockAlexandru Gagniuc
This bit is not documented in the datasheet, but is used in the upcoming RAM init code. Change-Id: I697ec222496236ac7690460ee62313ab8b1a2f0b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-08cpu/allwinner/a10: Add basic TWI (I²C) driverAlexandru Gagniuc
Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4588 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08cpu/allwinner/a10: Refactor API for gating clocks to peripheralsAlexandru Gagniuc
Rather than having to track which bit in which register should be cleared or set to gate or ungate the clock to a certain peripheral, provide a simplified enum which encodes the register and bit. This change comes with a function which decodes the enum and gates/ungates the clock. This also removes the register-dependent bitmasks for APB0 and APB1 gating registers. Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4571 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08cpu/allwinner/a10: Refactor and document pinmux APIAlexandru Gagniuc
Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4565 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08cpu/allwinner/a10: Clarify the usage of SRAM during bootblockAlexandru Gagniuc
We have 32KiB of usable SRAM right when we boot. The first 24KiB can be loaded with our bootblock, while the other 8KiB can be used as stack during the bootblock stage. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb Reviewed-on: http://review.coreboot.org/4563 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08mainboard: Add preliminary support for A10-based CubieboardAlexandru Gagniuc
Add a minimal infrastructure which initializes the system clocks and serial console. Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08cpu: Add initial support for Allwinner A10 SoCAlexandru Gagniuc
Add minimal support needed to get a bootblock capable of initialising a serial console. Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4549 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-06CBMEM: Fix allocation for static CBMEMKyösti Mälkki
CBMEM console buffer size is adjustable in menuconfig, but this would not correctly adjust the overall allocation made for CBMEM. HIGH_MEMORY_SIZE is aligned to 64kB and definitions are moved down in the header file as HIGH_MEMORY_SIZE is not used with DYNAMIC_CBMEM. Try to continue boot even if CBMEM cannot be created. This error would only occur during development of new ports anyways and more log output is better. Change-Id: I4ee2df601b12ab6532ffcae8897775ecaa2fc05f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4621 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-01-06CBMEM: Drop cbmem_base_check()Kyösti Mälkki
This function was for logging only, but we have both base and size already logged elsewhere. Change-Id: Ie6ac71fc859b8fd42fcf851c316a5f888f828dc2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06CBMEM ACPI: Move resume handlerKyösti Mälkki
Handler is ACPI/x86 specific so move details out of cbmem code. With static CBMEM initialisation, ramstage will need to test for S3 wakeup condition so publish also acpi_is_wakeup(). Change-Id: If591535448cdd24a54262b534c1a828fc13da759 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4619 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06usbdebug: Fix hidden menuconfig optionsKyösti Mälkki
Options for selecting the USB port and controller for usbdebug were unintentionally hidden with commit 8232bc2c on AGESA platforms using cimx/sb700 or cimx/sb800. Change-Id: Ibacc81a580519fe7fa86f08374046625327340b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4607 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-06MRC cache: determine flash size on runtimeVladimir Serbinenko
It should be possible to put coreboot compiled for smaller chip by putting it at the end of bigger chip. We already have chip size in flash->size. Use it. Tested on Lenovo X230. Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4612 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-06nehalem: Simplify smi.c by using __SIMPLE_DEVICE__Vladimir Serbinenko
Change-Id: Ib5bac45ee7aa5492c10fa97cd75b828b6192250d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-06cpu/cpu.h: Allow compiling with __SIMPLE_DEVICE__Vladimir Serbinenko
Change-Id: I14a2ac47198be6359b4f10b38f1cf86c9917d67e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4602 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-04X201: Fix native video initVladimir Serbinenko
Due to recent restructuring X201 native video init has disappeared from config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4606 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-04device/Kconfig: Add third person singular s to lacksPaul Menzel
Change-Id: I74be0dbbf8d99f58ac28bfac281ccd27d1500078 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4608 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-19 14:49:12 +0000