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2020-11-30mb/kontron/bsl6: Configure GPIOs using mainboard_opsFelix Singer
Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/intel/skylake: Fix commentFelix Singer
mainboard_silicon_init_params() is *not* meant for configuring GPIOs. It should only be used to configure FSP options, which can not be configured elsewhere. Change-Id: Ia92d0d173af9c67600e93b473480967304772998 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48008 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoCFelix Held
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in the corresponding SoC code, so remove it from the SoC's Kconfig and reanme it in the mainboard's Kconfig to MANDOLIN_LPC. Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30soc/amd/picasso: remove unused AMDFW_OUTSIDE_CBFS Kconfig optionFelix Held
The corresponding functionality in the SoC's Makefile.inc was removed in commit ef3395d990bbf1118a8d4e367a986bdbc92b1820 Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30soc/amd: move bootblock inside main SoC directoriesFelix Held
There's no need to have the bootblock in its own sub-directory, so move it to each SoC's main directory to avoid clutter. This makes soc/amd more consistent with the coreboot code base in src/northbridge, src/southbridge and src/soc with the exception of src/soc/intel. Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/volteer: Create drobit variantFrank Chu
Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/common/vboot: use transfer_buffer_valid functionFelix Held
show_psp_transfer_info reimplemented the functionality of transfer_buffer_valid, so use replace that with a function call. Change-Id: Ie3d373b10bdb0ab00640dabeea12b13ec25406cc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30soc/amd: move vboot-on-PSP-related functions to common/vbootFelix Held
Change-Id: I4f07d3ab12116229a13d2e8c02b2deb06e51a1af Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30soc/amd: move vboot bootblock functions to common folderFelix Held
Change-Id: I9e9fed26a686b8f90797687dd720902be48dae72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30soc/amd: move assembly part of non-CAR bootblock to common directoryFelix Held
There will be more files added to the common non-CAR Makefile.inc, so use an ifeq statement there. Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-30soc/amd/common: introduce SOC_AMD_COMMON_BLOCK_PCI_MMCONFFelix Held
Add a Kconfig symbol for including the PCIe MMCONF setup function in the build and select it when SOC_AMD_COMMON_BLOCK_PCI is selected and in the southbridges call enable_pci_mmconf(), but don't select SOC_AMD_COMMON_BLOCK_PCI. Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47878 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30drivers/intel/fsp2_0: Remove console in weak functionArthur Heymans
This pollutes the log on all platforms not implementing an override. Change-Id: I0d8371447ee7820cd8e86e9d3d5e70fcf4f91e34 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48128 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/dedede: Update Imon slope and Offset Value for DrawciaMeera Ravindranath
Updating Imon slope and offset values as per recommendation of ODM based on calibaration. Updating Imon slope to 1.0 and offset to 1.4 BUG=b:167294777 BRANCH=dedede TEST=Boot dedede platform and confirm values in FSP. Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-11-30mb/google/dedede: Create sasuke variantRaymond Chung
Create the sasuke variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:172104731 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKE Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-30lenovo/g505s: remove the unused and not present devicesMike Banon
Remove the devices unused or not present on this laptop. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-30mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHzFrank Chu
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/intel/alderlake: Add initial chipset.cbTim Wawrzynczak
Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30include/device/pci_ids.h: Fix device id for gspi2Bora Guvendik
Device ID for "D18:F6 - GSPI #2" shoud be 0xA0FB BUG=none TEST=Boot to OS, verify SSDT Signed-off-by: Selma BENSAID <selma.bensaid@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48060 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak
Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-30elog: Add new wake source codesTim Wawrzynczak
Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-30mb/google/volteer/variant/copano: Add memory part supportNick Vaccaro
Add support for the following 5 LPDDR4x memory parts: - MT53E512M64D4NW-046 WT:E - H9HCNNNCRMBLPR-NEE - MT53D1G64D4NW-046 WT:A - H9HCNNNFBMBLPR-NEE - MT53D512M64D4NW-046 WT:F DRAM Part Name ID to assign ------------------------------------------- MT53E512M64D4NW-046 WT:E 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) MT53D512M64D4NW-046 WT:F 0 (0000) BUG=b:172993397 TEST=none Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30lp4x: Add new memory parts and generate SPDsNick Vaccaro
Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. BUG=b:172993397 TEST=none Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-11-30mb/prodrive/hermes: Use PCH_DEV_SMBUS definitionAngel Pons
This allows dropping ugly preprocessor usage from this file. Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/prodrive/hermes: Encapsulate GPIO setupAngel Pons
Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30mb/prodrive/hermes: Use C-style commentsAngel Pons
Most of the existing comments are C-style already. Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30soc/amd/common: add comments and FIXME to Makefile.inc filesFelix Held
Change-Id: Ie347ee508acd900353467b4a3e0a5d1928b110e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47877 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/common: simplify conditionals in MakefilesFelix Held
If there are multiple statements that are conditional on the same Kconfig option, group them and move the condition check around the statement. If there's only one statement depending on one condition, use the short form instead. Change-Id: I89cb17954150c146ffc762d8cb2e3b3b374924de Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47876 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/common/block/cpu: move CAR-specific Makefile to sub-directoryFelix Held
Since there are sub-directories for both the cache-as-RAM case and the non-CAR case where the RAM is already initialized when the x86 cores are released from reset, move the CAR-specific parts of the Makefile.inc to another Makefile.inc in the car sub-directory. Further patches will add a Makefile.inc to the non-CAR directory. Change-Id: I43a3039237d96e02baa33488e71c5f24effe8359 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47875 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30drivers/intel/i210: Request Bus Master in .final opsAngel Pons
Commit bd31642ad8 (intel/i210: Set bus master bit in command register) is only necessary because a buggy OS expects Bus Master to be set, not because the hardware requires Bus Master during initialization. It is thus safe to defer the Bus Master request into the .final callback. Change-Id: Iecfa6366eb4b1438fd12cd9ebb1a77ada97fa2f6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47401 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot
2020-11-30mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()Angel Pons
There's one copy of this function for all variants except mc_apl4. Move one copy into common mainboard.c and exit early if running on mc_apl4. Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logicAngel Pons
A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is considered valid. Instead of using a temporary buffer and memcmp(), use a single loop that exits as soon as the MAC cannot possibly be invalid. Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-30drivers/intel/i210: Define MAC_ADDR_LENAngel Pons
Define and use the MAC_ADDR_LEN macro in place of the `6` magic value. Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-11-30mb/siemens/mc_apl1/mainboard.c: Refactor loop bodyAngel Pons
Break down multi-line compound conditions into multiple if-statements, and leverage `continue` statements to avoid nesting multiple checks. Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: siemens-bot Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
2020-11-29mb/google/volteer: eldrid: use devtree aliases for PMC MUX connectorsScott Chao
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:172528109 BRANCH=firmware-volteer-13521.B TEST=built and USB3.0, type-c display work. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh
This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29soc/intel/alderlake: Add lp5_ccc_config to the board memory configurationSridhar Siricilla
TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVPSubrata Banik
TEST=Able to pass MRC training on DDR4/5 SKUs Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-29mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_SERVERMichael Niewöhner
Set the FADT PM profile to ENTERPRISE_SERVER, since the currently supported X11 boards are server boards. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48088 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29mb/supermicro/x11-lga1151-series: rework gpio setup to not use headersMichael Niewöhner
Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-29mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.initMichael Niewöhner
GPIO needs to be initialized before the IPMI device gets initialized, so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus, use mainboard_ops.init for GPIO configuration instead of using the indirection via a mainboard_enable function. To make it more visible, that we use chip.init, rename `mainboard_init` to `mainboard_chip_init`. Tested successfully on X11SSM-F including the IPMI changes. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28mb/supermicro/x11ssm-f: drop unneeded ITSS overrideMichael Niewöhner
The ITSS override is not needed for LPC_CLKOUT* pads. Drop it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: configure gpios in mainboard initMichael Niewöhner
Move gpio configuration from the Fsp callback to mainboard init. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-28mb/supermicro/x11-lga1151-series: restructure and clean up devicetreeMichael Niewöhner
Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-28soc/intel/skl: correct OC pin skip value for disabled usb portsMichael Niewöhner
Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to supposedly skip programming an OC pin for a disabled USB port. While the value is correct for the other platforms, Skylake uses 0x08 for this purpose. Correct this by using the enum value OC_SKIP (0x08) instead. Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-27{docs/,}mb/supermicro/x11ssh-tf: drop TODO sectionMichael Niewöhner
Drop the TODO comment, since there is no TODO left. Also drop the now obsolete TODO section from the board documentation. Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-27Makefile.inc: Move adding mcu FIT entriesArthur Heymans
This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27soc/intel/jasperlake: Enable VT-d and generate DMAR TableMeera Ravindranath
Update UPDs required for the creation of DMAR table. By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error. BUG=b:170261791 BRANCH=dedede TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-11-26drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfigMichael Niewöhner
Move the FSP FD PATH option down, so it gets shown in place of the split FD files, when the users chooses to use a full FD binary. Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26drivers/intel/fsp2_0: introduce possibility of using a full FD binaryMichael Niewöhner
Currently, setting a custom FSP binary is only possible by using split FSP-T/M/S FD files. This change introduces the possibility to pass a combined FD file (the "standard" FSP format). This is done by adding a new boolean Kconfig FSP_FULL_FD, specifying that the FSP is a single FD file instead of split FSP-T/M/S FD files, and making FSP_FD_PATH user-visible when the option is chosen. In this case, the other options for split files get hidden. When the user chooses to use a full FD file instead of the split ones, the FD file gets split during build, just like it is done when selecting the Github FSP repo (FSP_USE_REPO). Test: Supermicro X11SSM-F builds and boots fine with custom FSP FD set. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-26vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11Subrata Banik
List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-19 08:46:23 +0000