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2016-01-28intel/strago: Disable unused devices.Divagar Mohandass
This change will disable unused devices in device tree to improve boot performance. TEST=Build/Flash CB and boot to OS. verify Touch screen, Audio, WIFI and Track pad functionality. Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/300943 Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Gomathi Kumar <gomathi.kumar@intel.com> Reviewed-on: https://review.coreboot.org/13423 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27soc/braswell: Fix leakage on V1P8S railShobhit Srivastava
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27soc/braswell: Add macro NATIVE_INT_PU20KHannah Williams
Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13054 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-27intel/strago: Fix GPIO configHannah Williams
Fix GPIO config for this board: - SD card detect to GPI - SATA GPI to not used - GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination - I2C4 SDA and SCL from not used to Native Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13431 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEnHannah Williams
Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27drivers/intel/fsp1_1: Enable builds without MRC cacheLee Leahy
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27intel/sklrvp: Remove mainboardMartin Roth
The Intel Skylake RVP3 mainboard is not building, and according to Intel, there is no plan to continue working on it for coreboot. The intel/kunimitsu board is the Skylake reference design for coreboot.org. Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13469 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-01-27chromeos: vpd: Avoid reading uninitialized VPDsJulius Werner
This patch adds a check to the VPD parsing code to avoid reading the whole thing if the first byte ('type' of the first VPD entry) is 0x00 or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types which should never occur as the first entry, so this usually means that the VPD FMAP section has simply never been initialized correctly. This early abort avoids wasting time to read the whole section from SPI flash (which we'd otherwise have to since we're not going to find a Google VPD 2.0 header either). BRANCH=None BUG=None TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to 1.5ms. Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720 Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322897 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/13467 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-27chromeos: Add timestamps to measure VPD read timesJulius Werner
This patch adds three timestamps to coreboot and the cbmem utility that track the time required to read in the Chrome OS Vital Product Data (VPD) blocks (RO and RW). It's useful to account for these like all other large flash accesses, since their size is variable. BRANCH=None BUG=None TEST=Booted Oak, found my weird 100ms gap at the start of ramstage properly accounted for. Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234 Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322831 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26arch/x86: Drop arch/pciconf.hStefan Reinauer
It's unused, so get rid of it. Change-Id: I28c6dc0208686edc3aabaf624773ea70350c1c8f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13177 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-26Braswell: Implement Gpio library functions to read RAMIDSubrata Banik
Added GPIO library code to allow all BSW board specific code to use memory configuration GPIOs in GPIO Input mode and read them to determine which memory type is on the board. Also added other GPIO related APIs to support GPIO access in BSW. Original-Reviewed-on: https://chromium-review.googlesource.com/294893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-26nb/intel/pineview: Increase MMCONF decoding to 256 bussesDamien Zammit
Linux kernel detects 256 busses but previously only 64 were allocated. Removes warning in OS. Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13033 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-26src/arch: Update license headers missing paragraph 2Martin Roth
For the coreboot license header, we want to use two paragraphs. See the section 'Common License Header' in the coreboot wiki for more details. Change-Id: I4a43f3573364a17b5d7f63b1f83b8ae424981b18 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13118 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-26ga-g41m-es2l: Instead of forcing native VGA, make it selectableMartin Roth
This allows the native VGA to be disabled for debug, or if someone wants to use the vbios. Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12848 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-01-26mainboard/intel/d510mo: Licence fixes and azalia verb tableDamien Zammit
Azalia verb table replicated from vendor bios. Licence headers added where appropriate. Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/12621 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-01-26arch/x86: move SetCodeSelector to .text segmentPatrick Georgi
It ended up in .data, and that doesn't seem to be actually necessary. Change-Id: Ib17d6f9870379d1b7ad7bbd3f16a0839b28f72c8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13134 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-25mc_tcu3: Enable auto generated attributes in cbfsWerner Zeh
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position and alignment attributes in cbfs. Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/13123 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-01-24nb/amd/mct_ddr3: Properly set MR0 WR valueTimothy Pearson
The existing code accidentally truncated the MSB from the MR0 WR value. While this probably had a minimal effect in reality, it should be configured correctly for maximal system stability. Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13147 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-24nb/amd/mct_ddr3: Add additional verbose-level debug statementsTimothy Pearson
Change-Id: Ie91c990d9c2bcab8292a75d87523a46d5694a34a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13146 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24nb/amd/mct_ddr3: Update drive strength configurationTimothy Pearson
The existing drive strength calibration code did not strictly follow the BKDG-defined setup process. Bring the calibration code in line with the BKDG recommendations. Change-Id: I122eeb93958d88de59d0c3b2979f607afa2c52c3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13145 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devicesTimothy Pearson
When an Extended Temperature Range DIMM is installed on a channel the refresh rate should be increased per the BKDG recommendations to allow correct operation at higher temperature ranges. Set fast refresh on a channel if an ETR DIMM is installed on that channel. Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24cpu/amd/family_10h-family_15h: Move CBMEM storage out of CC6 save regionTimothy Pearson
The existing CBMEM TOM calculations did not account for the CC6 save region (when enabled); this resulted in CBMEM storage being placed on top of the CC6 save region, which resulted in corrupt CBMEM data and a boot hang. Change-Id: I32399da0438d7b16e05192449be625f9aa675b18 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13143 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 socketsTimothy Pearson
The existing code unconditionally cleared the LDT tristate enable bit, which was incorrect for C32 sockets. Update the code to be in line with the BKDG recommendations. Change-Id: I8095931973ea10f1467a6621092e88c6c494565a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13142 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-24northbridge/amd/amdmct: Add termination and timing values for C32 socketsTimothy Pearson
The existing MCT initialization code was largely missing C32 socket- specific configuration data. Add C32 socket-specific timing and ODT values as specified in the BKDG. Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13141 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24northbridge/amd/amdfam10: Update DRAM speed limits for C32 socketsTimothy Pearson
The existing code applied G34-specific speed limits to all socket types. Update G34 and C32 specific speed limits to be in line with BKDG recommendations. Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13140 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24purism/librem13: Fix select of EC_PURISM_LIBREMMartin Roth
This was misspelled as EC_PURISM_LIBEM, causing the EC to not get included in the build. Change-Id: Iffbfb504926e1b90070c2dbf61c0c44ca8fb46bc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13178 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-23arch/x86: link bootblock like other stages for C_ENVIRONMENT_BOOTBLOCKAaron Durbin
When C_ENVIRONMENT_BOOTBLOCK is selected link bootblock using the memlayout.ld scripts and infrastructure. This allows bootblock on x86 to utilize all the other coreboot infrastructure without relying romcc. Change-Id: Ie3e077d553360853bf33f30cf8a347ba1df1e389 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13069 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-01-23lib/memrange: allow stack allocated free listAaron Durbin
Instead of solely relying on malloc for building up an address space for the range_entry objects allow one to supply a list of free entries to memranges_init_empty(). Doing this and only calling malloc() in ramstage allows a memranges oboject to be used in a malloc()-free environment. Change-Id: I96c0f744fc04031a7ec228620a690b20bad36804 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13020 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-23cpu/amd: remove .intel_syntaxPatrick Georgi
Replace with the more familiar AT&T syntax. Tested by sha1sum(1)ing the object files, and checking the objdump that the code in question was actually compiled. Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13133 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-23arch/x86: remove .intel_syntaxPatrick Georgi
Replace with the more familiar AT&T syntax. Tested by sha1sum(1)ing the object files, and checking the objdump that the code in question was actually compiled. Change-Id: Ie85b8ee5dad1794864c18683427e32f055745221 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13132 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22google/oak: Configurate SD card detection pinYidi Lin
BRANCH=none BUG=chrome-os-partner:47609 TEST=remove servo board connection and insert/remove an empty SD card in recovery mode. Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6 Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313073 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13099 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: revise cbmem_topCC Ma
Support memory range querying to above/below 4GiB. Enable PRERAM_CBMEM_CONSOLE. BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: If12ab2e9b8a129e2c82dd97b0493d9abdd6985a9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 139a3163ca867ec5676c6cb81fdec724c99a4a99 Original-Change-Id: Ie190f86f49ae88671f0738e2d6ceafdad58a93cc Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292559 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13098 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22mediatek/mt8173: move rtc_boot() to romstageYidi Lin
BRANCH=none BUG=none TEST=boot to kernel Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55 Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313969 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22lib: compile mdelay for romstagePatrick Georgi
Mimicking change I7037308d2, always compile mdelay for romstage. The boards that #included delay.c in the romstage now rely on the linker instead, which is a desirable cleanup. Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-22google/oak: setup usb and configure I2C level shift pinBen Lok
BRANCH=none BUG=none TEST=build pass and verified on rev3 Change-Id: I3849342e59c2b022db723ef0281cdd5153ae27cb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 495e978cd7381bd393099315ac6d60fe4446dd9f Original-Change-Id: I9626d06746e5d0bf6698a9b8e7594c58e7ff213a Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292689 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13096 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add usb phy driverChunfeng Yun
BRANCH=none BUG=none TEST=build pass and test it ok on oak Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23 Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292687 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13095 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: pll: Add API for enabling USB 3.0 phy reference clockChunfeng Yun
BRANCH=none BUG=none TEST=test it ok on oak-rev3 Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4 Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297942 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Configure backlight control pinsYH Huang
Since backlight is controlled in depthcharge, we only configure control pins as output pin and set them power-off in the coreboot stage. BRANCH=none BUG=none TEST=Saw DEV screen during boot process. Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754 Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292686 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13093 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: configure audioKoro Chen
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I01eb059a3525bbbc5d17335cf43bc01be4355142 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13092 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: configure audioKoro Chen
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13091 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: add APLL clock settingKoro Chen
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S. The function is called by mainboard's configure_audio(). BRANCH=chromeos-2015.07 BUG=chrome-os-partner:41507 TEST=build and verified pass on oak board Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6 Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297225 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13090 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add mtcmos power-on control for audio and displayCC Ma
BRANCH=none BUG=none TEST=none Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0 Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292677 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12617 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-01-22mediatek/mt8173: Add RTC driverTianping Fang
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af Original-Signed-off-by: Tianping Fang <tianping.fang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292676 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12616 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2016-01-22google/oak: Disable vboot mock data, now that I2C is functionalLiguo Zhang
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: I7a635c57ba271c8f568bd3334929acdf6a058ce8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32 Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292667 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13078 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add I2C driverLiguo Zhang
BUG=none TEST=emerge-oak coreboot BRANCH=none [pg: split into multiple commits] Change-Id: If2cac5aecc5675048e0e2d28897b1a82e099de7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32 Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d Original-Signed-off-by: liguo.zhang <liguo.zhang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292667 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12615 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Enable MMU supportJimmy Huang
BRANCH=none BUG=none TEST=build pass [pg: split into multiple commits] Change-Id: I6e165cfa6a8345de3d8d5461a75d5ed626ece4ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13077 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add MMU supportJimmy Huang
BRANCH=none BUG=none TEST=build pass [pg: split into multiple commits] Change-Id: Ib46b243102969e2860479070e19640fb6cb9bdd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock codeYidi Lin
The mt8173 boot rom expects the bootblock to be in a certain format. gen-bl-img wraps our bootblock appropriately. BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3 Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292664 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12613 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22google/oak: Add support for verstageItamar
Add support for verstage [pg: split original commit into multiple commits] Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-22mediatek/mt8173: Add support for verstageItamar
Add support for verstage [pg: split original commit into multiple commits] Change-Id: Ia43bc72a1fb36c6fad5be5654abee5fc19fc4093 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-20 06:23:56 +0000