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2020-06-02drivers/vpd: add VPD region VPD_RW_THEN_ROJonathan Zhang
This change is based on the concept that system user's (overwrite) settings are held in VPD_RW region, while system owner's (default) settings are held in VPD_RO region. Add VPD_RW_THEN_RO region type, so that VPD_RW region is searched first to get overwrite setting, otherwise VPD_RO region is searched to get default setting. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Icd7cbd9c3fb2a6b02fc417ad45d7d22ca6795457 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-06-02drivers/vpd: rename VPD_ANY to VPD_RO_THEN_RWJonathan Zhang
Rename VPD_ANY to VPD_RO_THEN_RW, to reflect the VPD region search preference. Update all existing code references for VPD_ANY. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41586 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependencyNico Huber
We want to use the CACHE_ROM_* macros in linker scripts. Avoid `commonlib/helpers.h` as it contains an ALIGN() macro definition that conflicts with the ALIGN keyword in linker scripts. Change-Id: I3bf20733418ca4135f364a3f6489e74d45e4f466 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02acpi: Add definitions for device sleep statesDuncan Laurie
The ACPI device sleep states are different from system sleep states and many places hardcode to specific values that are difficult to decode without referring to the spec. Change-Id: If5e732725b775742fd2a9fd0df697e312aa7bf20 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41791 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/volteer: Enable TCSS DMA0 for VolteerJohn Zhao
This explicitly enables TCSS DMA0 controller and disables TBT PCIe2 and PCIE3 since they are unused on volteer. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02mb/google/dedede: Enable GBB configs for dededeUsha P
This patch enables the necessary GBB configs for dedede BUG=none BRANCH=none TEST=GBB Flag value was 0x39 before enabling the required flags and now it is updated to 0x40b9. Verfied from CPU log. Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2020-06-02mb/google/dedede: Add SD card supportAamir Bohra
1. Configure SD card GPIOs. 2. Set SD card power polarity and card detect configs. SD card CMD. DATA and CLK GPIOs are set for native pad termination as per recommendation in EDS vol1 section 10.4.10 BUG=b:150872580 TEST=Verify SD card enumeration and read/write transactions. Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02mb/google/dedede: Enable coreboot lock down configAamir Bohra
TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-01soc/intel/common: Trigger recovery mode for CSE Lite SKU run time errorsSridhar Siricilla
Implement triggering recovery mode for CSE Lite SKU runtime errors. Also, define recovery subcodes for various possible Lite SKU runtime errors. BUG=b:153520354 TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib7744fc4fd0e41804d9b45079bf706b300220c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-01src: Fix up #-commented SPDX headersAngel Pons
Delete leading empty comment lines. Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-01sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bitsAngel Pons
Commit 73ae076 "fixed" accesses to the PCI command register that were not 16 bits, but also lost some bits to be written in the process. Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-06-01src: Fix up ##-commented SPDX headersAngel Pons
Delete leading empty comment lines. Change-Id: If1c5f568af3290c329d22dfc054d10d01c079065 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-01soc/intel/common/block: Remove unused headersAngel Pons
Change-Id: I8877a70661cacc57ea893da172d9a4b6d19ba06a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-01mb/asrock/b85m_pro4/cmos.layout: Remove copyright noticesAngel Pons
Change-Id: I2aaabec17073c0a2ccd40de068223a9215186db3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-01mb/asrock/e350m1: Do not redefine AGESA_VERSION_STRINGAngel Pons
This is the only AGESA f14 board which has a different version string. As it is most likely a copy-paste error, drop the redefinition of this macro from buildOpts.c and use the value defined in AGESA f14 headers. Change-Id: I384bd96db51457e68a320b99ecdbb2ada0dfbdd5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-01AGESA f14/f15tn/f16kb: Clean up buildOpts.c filesAngel Pons
Until now, the buildOpts.c files were primarily made out of copy-pasted AGESA options, commented-out definitions and several useless comments; that is, the materialization of technical debt in GCC-parsable form... Until now. It is assumed that the boards in the tree still boot. So, by comparing their settings, we can extract saner defaults to place into AGESA. Many of the settings were common across all boards of the same family, so we promote those values to default settings. In some cases flipping a flag was required, so the macros to alter that option had to be adapted as well. Since those AGESA versions are expected to never receive updates, it should not be a problem to change their files to suit our needs. As a result, all but two buildOpts.c files now have less than 100 lines. AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require about 60 or 70 lines in those files. Hopefully, this will make porting more mainboards using AGESA f14/f15tn/f16kb a substantially easier task. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2020-06-01mb/google/hatch: Add Noibat variantEdward O'Callaghan
A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-31soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda
This change updates pch_hda.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for Volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-31soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0Venkata Krishna Nimmagadda
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-30soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA controllers setting. BUG=:b:146624360 TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling. lspci shows TcssDma0(0d.2) and TcssDma1(0d.3). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/dedede: Enable Heci1 deviceAamir Bohra
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow. TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-29fit: Swap compat matching priorities for board-revX and board-skuYJulius Werner
Matching the same behavior change in depthcharge's FIT image code (CL:2212466), this patch changes the order in which compat strings involving revision and SKU numbers are matched when looking for a compatible device tree. The most precise match (board-revX-skuY) is still the highest priority, but after that we will now first check for revision only (board-revX) and then for SKU only (board-skuY). The reason for this is that SKU differentiation is often added later to a project, so device trees for earlier revisions may not have SKU numbers defined. So if we have a rev0 board (with sku0 as the "default SKU", because the board only started having different SKUs with rev1) we want it to match the board-rev0 device tree, not board-sku0 which was added as an alias to board-rev1-sku0 to provide the best known default for potential later revisions of that SKU. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia3cf7cbb165170e2ab0bba633fec01f9f509b874 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-05-29soc/amd/picasso: Enable FSP compressionFurquan Shaikh
This change enables LZMA compression for both FSP-M and FSP-S. This results in significant savings in the FSP size in each CBFS: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 132404 LZMA (720896 decompressed) fsps.bin 0xbdfc0 fsp 86146 LZMA (327680 decompressed) LZ4 works too, but the savings are smaller as compared to LZMA: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 189530 LZ4 (720896 decompressed) fsps.bin 0xcbfc0 fsp 118952 LZ4 (327680 decompressed) BUG=b:155322763,b:150746858,b:152909132 TEST=Verified that Trembyle boots to OS. No FSP-M or FSP-S errors in boot logs. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie5e4d58e671e936aa525d3000f890e9e5ae45ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-29soc/amd/picasso: Relocate FSP-M to address in DRAMFurquan Shaikh
On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16Marco Chen
The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is NT6AP256T32AV-J2 so the SPD content is generally extracted from it's SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's requirement. BUG=b:152277273 BRANCH=None TEST=build the image successfully. Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29mb/google/hatch: Select the fmd files for puff baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_PUFF and also renames the files to align with basebaord name and layout size. BUG=b:154561163 TEST=Built puff and verified that it selects the right fmd file. Change-Id: Ice6196ca778c6c118ce89e1510a445339a5c3455 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-29mb/google/hatch: Select the fmd files for hatch baseboardV Sowmya
This patch selects the fmd files based on config BOARD_GOOGLE_BASEBOARD_HATCH and also renames them to add the baseboard name and layout size tags. BUG=b:154561163 TEST=Built hatch variants and verified that they select the right fmd files. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I5d99ae28cc972ffa635adf100b756c36e168a8f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-29mb/google/hatch: Select BOARD_ROMSIZE_KB_16384 by defaultFurquan Shaikh
All hatch and puff variants use 16MiB SPI flash except the legacy ones which used 32MiB flash. Kconfig.name is updated to select BOARD_ROMSIZE_KB_32768 only for the legacy variants and BOARD_GOOGLE_HATCH_COMMON selects BOARD_ROMSIZE_KB_16384 by default if BOARD_ROMSIZE_KB_32768 is not selected. TEST=Verified using abuild --timeless that all hatch variants generate the same coreboot.rom image with and without this change. Change-Id: I708506182966936ea38562db8b0325470e34c908 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41662 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29AGESA boards: Fix typo in *OVERRIDES* in commentPaul Menzel
Run the command below to fix all occurrences. git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g' Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-05-29Puff: Disable EFS1 for variantsDaisuke Nojiri
VBOOT_EC_EFS is for EFS1 and EFS1 is deprecated. Puff uses EFS2 and its variants should follow. BUG=b:157372086 BRANCH=none TEST=emerge-puff coreboot Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I581f137b506a96df45e5bed21833856bb4f6aaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-28ec/google/chromeec: Switch to use new acpigen_usb moduleTim Wawrzynczak
Implementation of the ACPI objects for the Type-C Connector Class was added in the previous patch. This patch removes the functionality from the ChromeEC's SSDT generator, and uses acpigen_usb instead. TEST=Verified contents of SSDT are the same. Change-Id: Icdbcee1f989ee3146f7495e08fc13f9386791858 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28acpi: Add new file for implementing Type-C Connector classTim Wawrzynczak
The USB Type-C Connector Class in the Linux kernel is not specific to the ChromeOS EC, so this functionality is now split out into a separate file, acpigen_usb.c. Documentation about the kernel side is available at https://www.kernel.org/doc/html/latest/driver-api/usb/typec.html. Change-Id: Ife5b8b517b261e7c0068c862ea65039c20382c5a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41539 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28ec/google/chromeec: Add new *-switch properties to USBC.CONx devicesTim Wawrzynczak
The Linux ChromeOS EC driver now looks for 3 new properties under each USBC.CONx device contained within the ChromeOS EC device. These properties are just a reference to the device that controls the switches for USB 2/3 muxing, SBU lines, and CC lines. It uses the new function, soc_get_pmc_mux_device() to retrieve the device. Change-Id: I03cd83f9b2901b5583053fac8ab6eab64717a07d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40618 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Implement soc_get_pmc_mux_device()Tim Wawrzynczak
The ChromeOS EC is adding new entries to its USBC.CONx devices (see later patch), and it needs to get access to the PMC.MUX device so that its ACPI path can be retrieved. This provides a weak function to return NULL for all Intel SoCs except for Tiger Lake, which locates the device if it is found in the devicetree. Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28mb/google/volteer: Add PMC.MUX.CONx devices to devicetree for VolteerTim Wawrzynczak
Volteer's MUX connections are known, and can now be described in ACPI tables. Port 1 has the only oddity, with SBU lines staying fixed in the CC1 orientation. TEST=Dump SSDT tables on Volteer, and confirm (coalesced for brevity): Scope (\_SB.PCI0.PMC) { Device (MUX) { Name (_HID, "INTC105C") Device (CON0) { Name (_ADR, 0) Name (_DSD, Package() { Package () { "usb2-port-number", 9 }, Package () { "usb3-port-number", 1 }, }) } Device (CON1) { Name (_ADR, 1) Name (_DSD, Package() { Package () { "usb2-port-number", 4 }, Package () { "usb3-port-number", 2 }, Package () { "sbu-orientation", "normal" }, ... } } } Change-Id: Id361b2df07e87ad72b6a59a686977b3f424e8ecf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28soc/amd/picasso/soc_util: add comment on socket detection problemsFelix Held
At least some Pollock engineering samples return FP5 socket type while they are in fact FT5 socket type. Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: remove unused functionsFelix Held
soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or soc code. The same fuctionality is still provided by get_soc_type(). Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28drivers/intel/fsp2_0: add option to compress FSP-M in cbfsAaron Durbin
Allow the ability for chipset or mainboard to choose to compress FSP-M in cbfs using LZMA or LZ4 routines. However, only non-XIP platforms will support FSP-M compression. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-M compression options. On picasso FSP-M (debug builds) the following savings were measured: no-compression: fspm.bin 720896 none FSP_COMPRESS_FSP_M_LZ4: fspm.bin 138379 LZ4 (720896 decompressed) -80% FSP_COMPRESS_FSP_M_LZMA: fspm.bin 98921 LZMA (720896 decompressed) -86% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I5c88510c134b56a36ff1cd97a64b51ab2fea0ab0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28soc/intel/tigerlake: Generate PMC ACPI device at runtimeTim Wawrzynczak
In an attempt to help reduce the amount of static ASL files that are littered throughout the codebase, pmc.asl was converted to runtime SSDT generation instead. If future SoCs reuse the same PMC, then this function can be moved to soc/intel/common/block/pmc for example. TEST=Verified the following was in the decompiled SSDT: Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Tiger Lake IPC Controller") Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xFE000000, // Address Base 0x00010000, // Address Length ) }) } } Also the following found in linux's /var/log/messages: "acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC ACPI device was found and its _CRS was locatable. Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28mb/google/dragonegg: remove abandoned projectAaron Durbin
Dragonegg is no longer in development nor used. Remove it. Change-Id: Ida30dba662bc517671824f8b70b73b4856836e97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28drivers/intel/fsp2_0: add option to compress FSP-S in cbfsAaron Durbin
Allow the ability for chipset or mainboard to choose to compress FSP-S in cbfs using LZMA or LZ4 routines. To accomplish this fsp_load_component() is added as an assist for performing the necessary logic and allow the caller to provide the destination selection. Since the main cbfs decompression paths are utilized add the appropriate checks for including compression algorithms under the FSP-S compression options. On picasso FSP-S (debug builds) the following savings were measured: no-compression: fsps.bin 327680 none FSP_COMPRESS_FSP_S_LZ4: fsps.bin 98339 LZ4 (327680 decompressed) -70% FSP_COMPRESS_FSP_S_LZMA: fsps.bin 71275 LZMA (327680 decompressed) -78% BUG=b:155322763,b:150746858,b:152909132 Change-Id: I8aa5d8c1cbaf4d08f38a918a9031a2570bc5247e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28lib/cbfs: add cbfs_stage_load_and_decompress helperAaron Durbin
The LZ4 compressed stages assume in-place decompression. The constraints are validated in cbfstool for _stages_ such that they can be decompressed in place. However, that is only true for stages. As such, add a wrapper, cbfs_stage_load_and_decompress(), that handles the LZ4 stage loading case. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I9525a266250aa6c775283b598c09d4f40692db55 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41755 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28include/uuid.h: Add missing includeRaul E Rangel
uuid.h uses uint8_t which is provided by stdint.h. BUG=b:153675915 TEST=Fixed my compiler error. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idbec40f444d9df7587b9066faac65499415dae6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-28mb/google/zork/berknip: Replace full GPL header with SPDX linePatrick Georgi
Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28lib: Add strtok() and strtok_r()harshit
Add strtok() and strtok_r() to the library. Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com> Change-Id: Ic855b31669be1c274cbf247c53ffa6f74ec5bf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-05-28arch/x86: Fix id section in linker scriptKyösti Mälkki
Builds where RESET_X86_VECTOR is adjusted would create unintentionally large bootblock files since id section can move far away from .reset and .text. Some builds segfault or may try to create close to 4 GB large intermediate build objects. For cases where build is successful, id section would not reside within REGION(program) or REGION(bootblock). A proper fix to always place the ID data at the end of the coreboot.rom file is left as follow-up work. For now, just place id section below .reset. Change-Id: Idf0e4defcde6d5e264d4752cc93f4ffb6749d287 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-28arch/x86: Remove more romcc leftoversKyösti Mälkki
The sections .rom.* were for romcc and no longer used. Some romcc comments were left behind when guards were removed. Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-28soc/intel/jasperlake: Disable PAVP UPDRonak Kanabar
This patch will disable PAVP UPD, which is by default enabled in FSP. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/jasperlake: Correct GPIO community PID configurationAamir Bohra
Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify GPIO PM bits are correctly set through MS0x ACPI method. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3da4945e93605a297baff076295433164fdf613d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41721 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 13:34:10 +0000