coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-06-15	include/rules.h: Add vboot_before_bootblock to ENV_ROMSTAGE_OR_BEFORE	Martin Roth
2020-06-15	security/vboot: Add option to run verstage before bootblock	Martin Roth
2020-06-15	cpu/intel: Remove obsolete comment in CAR setup	Kyösti Mälkki
2020-06-15	arch/x86: Remove NO_FIXED_XIP_ROM_SIZE	Kyösti Mälkki
2020-06-15	arch/x86: Remove XIP_ROM_SIZE	Kyösti Mälkki
2020-06-14	soc/amd/picasso/graphics: implement map_oprom_vendev_rev	Martin Roth
2020-06-14	drivers/intel/fsp2_0: Add FSP 2.2 specific support	Subrata Banik
2020-06-14	mb/google/volteer: Disable HDA PCI device when AUDIO=NONE	Duncan Laurie
2020-06-14	mb/google/zork: Drop OEM_BIN configs	Furquan Shaikh
2020-06-14	mb/google/zork: Enable ELOG options	Furquan Shaikh
2020-06-14	southbridge/intel/common: Introduce ASL2.0 syntax	Alexey Buyanov
2020-06-14	soc/amd/picasso/aoac: Add wait_for_aoac_enabled	Raul E Rangel
2020-06-14	soc/amd/picasso/aoac: Set the Target Device State when powering on	Raul E Rangel
2020-06-14	soc/amd/picasso: Move aoac functions to new file	Raul E Rangel
2020-06-14	soc/amd/picasso: Explicitly disable legacy UART	Raul E Rangel
2020-06-14	console, PCI: Remove EARLY_PCI_BRIDGE support in verstage	Kyösti Mälkki
2020-06-14	mb/google/volteer/var/terrador: Update dq/dqs mappings	David Wu
2020-06-14	soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS	Jonathan Zhang
2020-06-14	soc/amd/picasso: correct MCFG ACPI table	Aaron Durbin
2020-06-14	mb/google/volteer: Enable thermal sensor 4 in DPTF for volteer	Deepika Punyamurtula
2020-06-14	dptf: Introduce new paradigm for configuring DPTF parameters	Tim Wawrzynczak
2020-06-14	soc/intel/tigerlake: enable CPU_INTEL_COMMON	Alex Levin
2020-06-14	soc/amd/picasso: Increase SMM_RESERVED_SIZE	Marshall Dawson
2020-06-14	mb/google/puff: add MST and LSPCON details to devicetree	Shiyu Sun
2020-06-14	soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake	Paul Menzel
2020-06-14	soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add cpu entries in ssdt	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: fix MADT ACPI table	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add IIO stack resources to DSDT	Jonathan Zhang
2020-06-14	soc/intel/xeon_sp/cpx: add NUMA ACPI tables	Jonathan Zhang
2020-06-14	mb/google/hatch/vr/puff: Set up PL2 and PsysPL2	Tim Chen
2020-06-14	mb/google/fizz: add variant chipset display init	Jeff Chase
2020-06-14	mb/google/dedede: Enable early EC software sync	Meera Ravindranath
2020-06-14	mb/google/dedede: Select Recovery Cache Kconfig option	Meera Ravindranath
2020-06-14	sb/intel/i82801ix: Fix SPDX license header	Kyösti Mälkki
2020-06-14	mb/google/hatch: Switch USB2 port1 and port3 on Noibat	Edward O'Callaghan
2020-06-14	soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1	Furquan Shaikh
2020-06-14	ec/google/chromeec: Call \PNOT () on initializing AC power state	Furquan Shaikh
2020-06-13	cpu/intel/car: Use symbols for CAR MTRR setup	Kyösti Mälkki
2020-06-13	arch/x86: Add symbols for CAR MTRRs in linker script	Kyösti Mälkki
2020-06-13	soc/intel/common: Introduce ASL2.0 syntax	Alexey Buyanov
2020-06-13	arch/x86: Include id.ld unconditionally in memlayout.ld	Furquan Shaikh
2020-06-13	arch/x86: Drop early_ram.ld	Furquan Shaikh
2020-06-13	soc/amd/picasso: Place early stages and data buffers at the bottom of DRAM	Furquan Shaikh
2020-06-13	cbmem_id: Add CBMEM ID for early DRAM usage	Furquan Shaikh
2020-06-13	soc/amd/picasso: Add custom memlayout.ld file	Furquan Shaikh
2020-06-13	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	Furquan Shaikh
2020-06-13	mb/google/zork: update DRAM SPD table for vilboz	Paul Ma
2020-06-12	mb/google/volteer/var/voxel: Add memory parts and generate DRAM IDs	Furquan Shaikh
2020-06-12	vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197	Srinidhi N Kaushik