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2021-01-28soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin
Initialize pmif_arb in romstage. BUG=b:177389446 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I3ffe7277c9ecb04269c832693d42799ba1711384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency. Usage: mt_pll_raise_cci_freq(1400UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28mb/google/dedede/var/sasuke: Configure GPP_G7 as nativeSeunghwan Kim
Configuring GPP_G7 as NC causes SD card detection issue on sasuke. So we'd like to remove the GPP_G7 override and keep the baseboard configuration as native function (SDIO_WP). BUG=b:175831709 BRANCH=firmware-dedede-13606.B TEST=Built and verified SDR104 SD card operation on sasuke Change-Id: If73337b482f04fd263caaa6fed0e54aa87bd876e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28bayhub bh720: Factor out common HS200 init codeAngel Pons
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28drivers/elog: Correct code styleFrans Hendriks
lint report errors Solve the POINTER_LOCATION errors BUG = N/A TEST = N/A Change-Id: I65926abd6bbaff1efce39efad9ec92c4f364b533 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49971 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/intel/common/fsb.c: Correct code styleFrans Hendriks
lint report warning Solve the RETURN_VOID BUG = N/A TEST = N/A Change-Id: I3b8088494049b5c3244531a4a77af4153edbdff4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/amd/agesa/family15tn/fixme.cFrans Hendriks
lint report errors and warnings Solve the next issues: - BRACES BUG = N/A TEST = N/A Change-Id: I27a712ec93c216fc3aa836baa53d6e2f2e68d3a3 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-01-28mb/google/asurada: Add config for spherionYu-Ping Wu
BUG=b:178440482 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ica09b73f97509db065c93c6be757c0d77c9b7a87 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28mb/emulation/qemu-i440fx: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46077 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/emulation/qemu-q35: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/google/volteer: Add GL9755 support to DrobitWayne3_Wang
Add the GL9755 support to drobit and also fixes the S0ix can't into C3~C9 problem BUG=b:174348200 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I52df6b2cdebfaf8a5eb010c4af1a2cf3d918f5e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49921 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/google/brya: Add variants overridetree.cb path and remove unused registersEric Lai
Add variants overridetree.cb path remove unused registers BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28mb/google/zork: add MST details to trembyle devicetreeShiyu Sun
Added device hid info to the MST RTD2141b device on trembyle. BRANCH=zork BUG=b:147402710 TEST=Build and flash BIOS image, see 10EC2141 appears under /sys/bus/i2c/devices Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-01-28soc/intel/xeon_sp/skx: Add soc_acpi_nameMarc Jones
Add the soc_scpi_name to the soc pci_ops. This is used by ACPI table generation and required by the intel common XHCI device. Change-Id: Idc09d53f14dfb1e42f904dfd4e87e8c09e155135 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2021-01-28mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28arch/x86/smbios: Update SMBIOS type 16 Extended Maximum CapacityTim Chu
Update Extended Maximum Capacity field in SMBIOS type 16 so that maximum dimm size can be over 2TB. Tested=Execute "dmidecode -t 16" to check maximum capacity is over 2TB. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I61901c815f9d0daae102e5077a116c0de87240ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/49828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-28acpi/acpigen.c: Remove unused and incorrect functionsJakub Czapiga
acpigen_write_name_zero() and acpigen_write_name_one() are not implemented correctly, and are not used anywhere. Drop them in favor of the more flexible acpigen_write_name_integer() function. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I116fd41624a8e8b536d18d747f21d3131b734dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Declare GNVS variables globallyKyösti Mälkki
There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limitsKyösti Mälkki
With top-aligned bootblock this is no longer globally needed. The default maximum is now a generous 256 KiB with couple platforms having lower limits of 32 KiB and 64 KiB. Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28arch/x86: Top-align .text in bootblockKyösti Mälkki
Move .text section closer to .init. This reduces the size of the flat bootblock binary and footprint in CBFS. Change-Id: I64325bd633e1104853cfb928c7f801d94ff3045a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28arch/x86: Top-align .init in bootblockKyösti Mälkki
Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Rename __protected_start symbolKyösti Mälkki
It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry32.incKyösti Mälkki
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Link reset16.incKyösti Mälkki
Change-Id: If2caab67286cf77e37928e03be4f581070e771d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47968 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/x86: Link entry16.incKyösti Mälkki
Change-Id: I78ecd15716169b58cf6696ff8c5069ac2d5038ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47967 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Refactor acpi_wake_source()Kyösti Mälkki
Change-Id: I44cb499260fdd0ea37308909a24cdf5ca1afa025 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Refactor fill_acpi_wake()Kyösti Mälkki
Change-Id: I7fcc2b36cfe57adf8ae3a6acf8b54e19504202a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49878 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/intel/adlrvp: Remove ClkReq assignment for RP8Subrata Banik
CLKSRC6 for RP8 is free-running CLK hence ClkReq is not required. TEST=Able to detect PCIe SD card over x1 slot. Change-Id: I550d5be9cc7566708b0b86fcd1da833bc4bc828f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28mb/intel/shadowmountain: Add flash layoutV Sowmya
This patch adds the flash layout for shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I7073d9c783684051e33e7a33eca50007d286bb00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-01-28soc/amd/picasso/acpi: Fix PCI0 MMIO windowRaul E Rangel
The PCI0 MMIO window was defined between TOM and 4 GiB. This was overlapping with the FCH MMIO devices. The first MMIO device after TOM is the FCH IOAPIC. This wasn't causing a problem for linux other than the fact that /proc/iomem showed all the MMIO devices under the PCI root bridge. On Windows this was causing all the MMIO devices to have conflicting resource errors. BUG=b:175146875 BRANCH=zork TEST=Boot linux and verify peripherals all work. Boot windows and verify the i2c controllers show up. The GPIO controller still has a problem related to power. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso: fix CBFS MCACHE on ZorkKangheui Won
Zork platform was not booting with MCACHE enabled since psp_verstage had following issues with MCACHE. Fix all the issues and re-enable MCACHE for Zork. * psp_verstage should call vboot_run_logic, not verstage_main. vboot_run_logic calls after_verstage which handles RW MCACHE build. * It should avoid low-level apis for cbfs access. cbfs_map will build RO MCACHE if it's the first stage, while other low-level apis won't. * It should call update_boot_region before save_buffers MCACHE should be transferred to x86 so we should build it before calling save_buffers BUG=b:177323348 BRANCH=none TEST=boot Ezkinil Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso/acpi: Remove DMA addresses for UARTsRaul E Rangel
This is not the correct way to specify the FixedDMA devices. I'm removing for now since it adds confusion. BUG=none BRANCH=zork TEST=Boot zork to linux and make sure UART still works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-28soc/amd/cezanne/chip: add empty SoC device operationsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6321223b3b4b8d27ac696fdeeec75fd4bd1e6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49952 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne: compress FSP binaries in CBFSFelix Held
Compressing the FSP binaries in CBFS reduces the load time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0faf9a3937e4a5027eba6327a51060025971450f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49951 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28Revert "mb/amd/mandolin: Clean up IRQ numbers"Felix Held
This reverts commit 2a1638a9cead257115ff82b18862d506015378b2. The original commit broke Mandolin and with the revert applied, I can boot into Linux via SeaBIOS again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7024b6ff1e772bbc89f810c766655a5887ed8b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49950 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons
Avoid indirect header inclusion, include `pch.h` where necessary. Change-Id: I6b72976a28ffaad68bcf558c8a13b5c221070522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-27soc/amd/picasso/chip: use switch/case statement in enable_dev()Felix Held
The default case is only needed to make the compiler happy. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27soc/amd/stoneyridge: Change set_sb_nvs_final()Kyösti Mälkki
Change-Id: I0de8033bae8c1dcfbc6fd7655ba748a3514e74e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/cezanne: Add UCODE firmware to CBFSZheng Bao
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/picasso: Remove the useless definition of UCODE_FILEsZheng Bao
UCODE files are integrated in CBFS now, instead of AMD firmware group. Change-Id: I88fdd08ab400fad8e323251bb7dab4e4e01b0b88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27soc/amd: Throw an error if FWM_POSITION_INDEX is emptyZheng Bao
The empty string causes an undetectable build error. Filter out the board which doesn't define this variable. A great odds that the reason is the board doesn't set a valid ROM size. Change-Id: Iade1961460285acdec245c553c7b84014c30c267 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27mb/google/brya/var/brya0: Use auto-generated Makefile.incAmanda Huang
This change adds mem_list_variant.txt that contains the only memory parts used by brya0 for Proto-0 build and Makefile.inc generated by gen_part_id.go using mem_list_variant.txt. BUG=b:176491791 Change-Id: I3fe755564e7541a7abdfca0e5aa7fd786f5ca880 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-27soc/intel/alderlake: Generate LP4x SPD files using gen_spd.goAmanda Huang
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with ADL-based mainboards. BUG=b:176491791 Change-Id: Ie75e43833bf9ba6557fc59cf8b4a0358d495e56a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49919 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-27soc/amd/common: Only set write_acpi_tables if ACPI table is enabledZheng Bao
In ./include/device/device.h, the struct device_operations is defined as below. ------------------------------------ #if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); #endif ------------------------------------ So we also need to add the same #if in the C source. Change-Id: I488eceacb260ebe091495cdc3448c931cc4a1ae3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27mb/google/dedede/var/sasukette: Generate SPD ID for supported memory partschenzanxi
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: K4U6E3S4AA-MGCR BUG=None TEST=Build the sasukette board. Change-Id: I57c9d22ae655032120f19add98ef454853428af5 Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-01-27ACPI: Separate device_nvs_tKyösti Mälkki
Remove typedef device_nvs_t and move struct device_nvs outside of global_nvs. Also remove padding and the reserve for chromeos_acpi_t. Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 05:38:41 +0000