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2020-10-17vc/amd/Kconfig: Add missing dot in AMD domain www.amd.comPaul Menzel
Fixes: b266c6b5 ("AMD Steppe Eagle: Add binary PI vendorcode files") Change-Id: Id317b53cfafaae629c2a94144c419e2112eaf7a9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17superio/nuvoton: Only set bit 7 of global CR 0x2a for COM APaul Menzel
Currently, when selecting SUPERIO_NUVOTON_NCT*_COM_A, the whole global control register 0x2a is written to 0x40. CR 0x2a defaults to 0xc0, so indeed bit 7 is cleared, but the device early init code might have set other bits in that control register, so setting it to 0x40 might override already set bits. So, only clear bit 7 and leave the other bits untouched. Fixes: f95daa510d ("superio/nuvoton: Add back Nuvoton NCT6776 support") Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-17intel/txt: Add `txt_get_chipset_dpr` functionAngel Pons
Due to platform-specific constraints, it is not possible to enable DPR by programming the MCH's DPR register in ramstage. Instead, assume it has been programmed earlier and check that its value is valid. If it is, then simply configure DPR in TXT public base with the same parameters. Note that some bits only exist on MCH DPR, and thus need to be cleared. Implement this function on most client platforms. For Skylake and newer, place it in common System Agent code. Also implement it for Haswell, for which the rest of Intel TXT support will be added in subsequent commits. Do not error out if DPR is larger than expected. On some platforms, such as Haswell, MRC decides the size of DPR, and cannot be changed easily. Reimplementing MRC is easier than working around its limitations anyway. Change-Id: I391383fb03bd6636063964ff249c75028e0644cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46490 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS]Angel Pons
The BIOS ACM will check that enabled variable MTRRs do not cover more than the ACM's size, rounded up to 4 KiB. If that is not the case, launching the ACM will result in a lovely TXT reset. How boring. The new algorithm simply performs a reverse bit scan in a loop, and allocates one MTRR for each set bit in the rounded-up size to cache. Before allocating anything, it checks if there are enough variable MTRRs; if not, it will refuse to cache anything. This will result in another TXT reset, initiated by the processor, with error type 5: Load memory type error in Authenticated Code Execution Area. This can only happen if the ACM has specific caching requirements that the current code does not know about, or something has been compromised. Therefore, causing a TXT reset should be a reasonable enough approach. Also, disable all MTRRs before clearing the variable MTRRs and only enable them again once they have been set up with the new values. Tested on Asrock B85M Pro4 with a BIOS ACM whose size is 101504 bytes. Without this patch, launching the ACM would result in a TXT reset. This no longer happens when this patch is applied. Change-Id: I8d411f6450928357544be20250262c2005d1e75d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44880 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACMAngel Pons
When caching the BIOS ACM, one must cache less than a page (4 KiB) of unused memory past the end of the BIOS ACM. Failure to do so on Haswell will result in a lovely TXT reset with Class Code 5, Major Error Code 2. The current approach uses a single variable MTRR to cache the whole BIOS ACM. Before fighting with the variable MTRRs in assembly code, ensure that enough variable MTRRs exist to cache the BIOS ACM's size. Since the code checks that the ACM base is aligned to its size, each `one` bit in the ACM size will require one variable MTRR to properly cache the ACM. One of the several BIOS ACMs for Haswell has a size of 101504 bytes. This is 0x18c80 in hexadecimal, and 0001 1000 1100 1000 0000 in binary. After aligning up the BIOS ACM size to a page boundary, the resulting size is 0x19000 in hexadecimal, and 0001 1001 0000 0000 0000 in binary. To successfully invoke said ACM, its base must be a multiple of 0x20000 and three variable MTRRs must be used to cache the ACM. The MTRR ranges must be contiguous and cover 0x10000, 0x8000, 0x1000 bytes, in order. The assembly code is updated in a follow-up, and relies on these checks. Change-Id: I480dc3e4a9e4a59fbb73d571fd62b0257abc65b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46422 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17trogdor/sc7180: Clarify USE_QC_BLOBS requirementsJulius Werner
This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-10-16include/cpu/x86: introduce new helper for (un)setting MSRsMichael Niewöhner
msr_set_bit can only set single bits in MSRs and causes mixing of bit positions and bitmasks in the MSR header files. Thus, replace the helper by versions which can unset and set whole MSR bitmasks, just like the "and-or"-helper, but in the way commit 64a6b6c was done (inversion done in the helper). This helps keeping the MSR macros unified in bitmask style. In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get added. The few uses of msr_set_bit have been replaced by the new version, while the used macros have been converted accordingly. Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16soc/intel/skylake: Rename PcieRpAspm devicetree configBenjamin Doron
This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-16acpi/acpigen_dsm: fix I2C HID DSM to report correct function supportJosie Nordrum
Fix DSM function 0 (query function) to correctly report function support for its revision. Revision 1 should return 0x3 because I2C HID supports only 1 additional function. All other revisions should return 0. BUG=b:170862147 BRANCH=Zork TEST=ensure no dmesg errors; disassemble and verify SSDT Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Iee082ef5cf44c4cf7ab304345af56f3b5173ca56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46429 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-16mb/google/zork: disable eMMC per FW_CONFIG for berknipKevin Chiu
Berknip has SSD/eMMC SKU, we should turn off eMMC　if storage is NVMe SSD. BUG=b:170592992 BRANCH=zork TEST=1. emerge-zork coreboot 2. Check eMMC is enabled or disabled based on the eMMC bit in FW_CONFIG. Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-10-16mb/intel/adlrvp: Enable Hybrid storage modeSubrata Banik
TEST=Build and test booting ADL RVP form NVMe and Optane localhost ~ # lspci -d :f1a6 Show all the NVMe devices and be really verbose localhost ~ # lspci -vvvd :f1a6 Print PCIe lane capabilities and configurations for all the NVMe devices. Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Enable PCIE RP11 for optaneSubrata Banik
A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width. Optane memory module shows up as 2 NVMe devices in x2 config: - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs because of same M.2 slot. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Fix SSD detection issue on ADL RVPSubrata Banik
Make PCI ClkReq-to-ClkSrc mapping correct to fix SSD detection issue on ADL RVP. TEST=Able to detect WD SSD card over PCH SSD RP9. Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-16mb/intel/adlrvp: Program GPIO for M.2 PCH SSDSubrata Banik
This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-15lib and libpayload: Add popcnt functionsAngel Pons
Add 32-bit `popcnt` and 64-bit `popcnt64` helpers. Change-Id: I2e6a1007e475b662a85c067d96f81326e7f02905 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-15soc/intel/xeon_sp: Add get_system_memory_map()Marc Jones
Prepare for common ACPI. Add get_system_memory_map() helper function to soc_util.c and use it in the SRAT ACPI code to match the cpx code. Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15ec/google/chromeec: Update ec_commands.hYidi Lin
This change copies ec_commands.h from Chromium OS EC repo at 7b6cb69db. The change also drops unneeded empty lines and coverts license header to SPDX style. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I9816dab5edb418e76896355a0802c59307c664c4 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-15Update bit field helpers to support more bit field operateHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I8f182fff45806912da2390939a6652932501d7c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-10-15sec/intel/txt/getsec_enteraccs.S: Save and restore MTRR_DEF_TYPEArthur Heymans
This needs to be saved and restored, otherwise the BSP might have an inconsistent MTRR setup with regards to the AP's which results in weird errors and slowdowns in the operating system. TESTED: Fixes booting OCP/Deltalake with Linux 5.8. Change-Id: Iace636ec6fca3b4d7b2856f0f054947c5b3bc8de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15nb/intel/haswell: Account for DPR region in memory mapAngel Pons
While MRC.bin does not allocate any memory for DPR by default, it can be patched to do so. However, the current northbridge code does not account for DPR and will, among other things, place CBMEM inside it. Even though this may seem like a good thing, it renders TianoCore unable to boot and clashes with Intel TXT support (the reason to enable DPR to begin with). Update memmap.c so that CBMEM top does not fall within DPR. Also, report DPR as reserved, so that OSes know that the DPR memory is not to be used. Change-Id: I11f23fd43188f987e35fd61f52587e567496cd78 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-15security/intel/txt: Use `smm_region()` to get TSEG baseAngel Pons
This function is available for all TXT-capable platforms. Use it. As it also provides the size of TSEG, display it when logging is on. Change-Id: I4b3dcbc61854fbdd42275bf9456eaa5ce783e8aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-15soc/intel/skylake: Configure L1 substates for PCH root portsBenjamin Doron
Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-14soc/intel/skylake/cpu.c: Fix comment coding styleAngel Pons
This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style. Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/google/volteer: Disable HybridStorageMode for volteer baseboardShaunak Saha
HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer baseboard. For boards using optane HybridStorage needs to be enabled from overwrite devicetree. We are enabling HybridStorage for volteer and volteer2 as those plaforms have SKU's with optane storage. BUG=b:158573805 TEST=Build and boot non optane device and confirm that FspSiliconInit time is reduced. This saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14lib and libpayload: add 64-bit versions of clz, __ffs and log2Tim Wawrzynczak
Add 64-bit versions of clz, __ffs & log2: `__ffs64`, `__clz64`, and `log2_64`. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iefc6e6c51f5b20607c88e38660a499a4f77ce0d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-14mb/intel/adlrvp: Add ADL-P mainboard ASL codeSubrata Banik
Add required ASL files into dsdt.asl TEST=Dump and disassemble DSDT and verify all ACPI devices are present. Change-Id: I70829e2bdb12fad20627d9aea47e745d9095f07a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/intel/adlrvp: Add ADL-P ramstage mainboard codeSubrata Banik
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14soc/intel/jasperlake: Enable CAR NEM enhanced modeAamir Bohra
TEST=Build and boot waddledoo board Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I067b13acfcea940e2e4ae6fc99b5d77458de35a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14nb/intel/x4x: Place raminit definitions in raminit.hAngel Pons
There's no need to have implementation details in a public header. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I04d8c610d3e52adecfe96cc435f0523bedf3060a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-14nb/intel/x4x: Move register headers into a subfolderAngel Pons
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I74dbd985b980d8a42bfaf2984820005320a803d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45421 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/purism/librem_skl: Drop DQ and DQS byte mapsAngel Pons
These settings are not necessary for DDR4 and can be dropped. Change-Id: I1946be239f0c90db995a60570474039cef45cfa9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-14nb/intel/x4x: Clean up DMIBAR/EPBAR definitionsAngel Pons
Several registers have been copy-pasted from i945 and do not exist on Eagle Lake. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I9582d159aa2344bcf261f0e4b97b15787156f6e7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-14soc/intel/broadwell/xhci.c: Align with Lynx PointAngel Pons
Change-Id: Idf40e2687b064c5ec7834e3c7d7ea9c8cb83c882 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45721 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/smi.c: Drop unused functionsAngel Pons
These aren't used anywhere, so get rid of them. Change-Id: I267c0fd2e9d9d20ee852a73a9a916d85d6c65088 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45716 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/pcie.c: Add some null checksAngel Pons
These are present in Lynx Point. Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14haswell/lynxpoint: Align cosmetics with BroadwellAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell: Align cosmetics with Haswell/Lynx PointAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13v1 does not change. Change-Id: Icf41d9db20e492ec77a83f8413ac99a654d6c8ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45697 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/broadwell/igd.c: Rename to gma.cAngel Pons
This makes comparisons against Haswell a bit simpler. Change-Id: If1c937628f702c6765a5f36b6eaf4a3c3516359a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14acpi/device: Add GPIO binding property for an array of GPIOsKarthikeyan Ramasubramanian
This change is required for use-cases like GPIO based I2C multiplexer where more than one GPIOs are used as select lines. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that the GPIO bindings for an array of GPIOs are added to the ACPI table as follows: Device (MUX0) { ... Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0125 } GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0126 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "mux-gpios", Package (0x08) { \_SB.PCI0.I2C3.MUX0, Zero, Zero, Zero, \_SB.PCI0.I2C3.MUX0, One, Zero, Zero } } } }) } Change-Id: I7c6cc36b1bfca2d48c84f169e6b43fd4be8ba330 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14mb/google/dedede/var/madoo: Update DPTF settingJohn Su
Add tcc, critical, passive policy, and pl values from thermal team. BUG=b:169215576 TEST=build and verify by thermal tool Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-10-14src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)Divya Sasidharan
EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIs added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST=Built coreboot image and verified that using this patch mux is being set for display during boot Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14soc/intel/common/block: Enable PMC IPC driverBrandon Breitenstein
In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:151731851 BRANCH=none TEST=built coreboot image and booted to Chrome OS Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-14mb/intel/tglrvp: Enable Pcie WWAN m.2Bora Guvendik
Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration. BUG=none TEST=Boot to OS, check WWAN functionality Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14mb/google/zork: Enable wake on wireless lanRob Barnes
Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up BRANCH=zork Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/alderlake: Enable TME for Alder LakeSubrata Banik
List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01Subrata Banik
List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/tigerlake: Enable and use USB4 PCIe driverDuncan Laurie
This change enables the USB4/Thunderbolt common layer for Intel SOC, and enables the Intel USB4 PCIe driver. This moves the _DSD variables from the DSDT into the SSDT and allows them to be configured for each board if necessary. Change-Id: I2564512d951046e015c148db42fdaf2d4b8b81dd Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44917 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/common: Add SSDT generation for Intel USB4 PCIe portsDuncan Laurie
This driver will generate the ACPI _DSD for the USB4 PCIe root port properties instead of using static ASL. It assigns the USB4 port number and marks the port as external and hotplug capable. Change-Id: I7086b06346ce63fab6bef4077fb76ae1d30dc1eb Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44915 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14soc/intel/common/block: Add common support for USB4/ThunderboltDuncan Laurie
This common intel driver will add the requried ACPI _DSD entries for enabled USB4/Thunderbolt ports' DMA devices the SSDT instead of using hardcoded values in the DSDT. Change-Id: Ic4a58202d4569cf092ea21a4a83a3af6c42ce9d0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-14soc/intel/common: Add PCI driver for USB4 portsTim Wawrzynczak
In order to enable SSDT generation for the DMA component of Intel USB4 ports, a PCI driver is required. This patch more or less adds a `scan_bus` callback that will handle non-PCI devices downstream. Change-Id: Ib9da051307b883eb99e500114378c9fd842ffc92 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 17:24:36 +0000