coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-08-08	vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc	Jonathan Zhang
2020-08-08	mb/google/zork/trembyle: comment why USB OC pin mapping is different	Felix Held
2020-08-08	soc/intel/skylake: Enable CIO depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Enable SA IMGU depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Add IMGU definitions to pci_devs.h	Felix Singer
2020-08-08	soc/intel/skylake: Enable SDXC depending on devicetree configuration	Felix Singer
2020-08-08	mb/asrock/h110m: remove unused Device4Enable from devtree	Maxim Polyakov
2020-08-08	soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192	CK Hu
2020-08-07	mb/google/zork: Revert Don't expose reset GPIO for touchscreen to OS	Martin Roth
2020-08-07	soc/intel/skylake: Enable thermal subsystem depending on devicetree	Felix Singer
2020-08-07	soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.h	Felix Singer
2020-08-07	soc/intel/cnl: Set Heci1Disable depending on devicetree config	Felix Singer
2020-08-07	soc/amd/picasso/acpi: remove AOAC device enables from global NVS	Felix Held
2020-08-07	xeon_sp/cpx: Enable HWP Intel Speed Shift	Johnny Lin
2020-08-07	soc/intel/broadwell/iobp: Log success in `pch_iobp_write()`	Angel Pons
2020-08-07	security/intel/txt: Fix variable MTRR handling	Angel Pons
2020-08-07	sb/intel/lynxpoint: Use PCI bitwise ops	Angel Pons
2020-08-07	sb/intel/lynxpoint: Consider root ports being disabled by strap	Angel Pons
2020-08-07	mb/elmex/pcm205401: Add comment about the code	Angel Pons
2020-08-07	mb/asrock/b85m_pro4: Support LPC TPM	Angel Pons
2020-08-07	security/intel/txt: Allow using CF9 reset, too	Angel Pons
2020-08-07	mb/intel/kblrvp: Factor out `IoBufferOwnership`	Angel Pons
2020-08-07	mb/intel/kblrvp: Factor out `HeciEnabled`	Angel Pons
2020-08-07	soc/intel/common: Log CSE FW Status Registers before triggering recovery	Sridhar Siricilla
2020-08-07	mb/google/volteer: support variant defined spd paths	Nick Vaccaro
2020-08-07	soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE	Subrata Banik
2020-08-07	Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings"	Paul Fagerburg
2020-08-07	src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INIT	Subrata Banik
2020-08-07	mb/google/dedede/var/magolor: Select 16 MB SPI ROM	Ren Kuo
2020-08-06	gpio: Pull down HiZ pins after reading tristate GPIO strapping	Julius Werner
2020-08-06	cpu/intel/common: Add `intel_ht_supported` function	Angel Pons
2020-08-06	mb/google/volteer/var/halvor: Update dq/dqs mappings	Amanda Huang
2020-08-06	mb/google/zork: Configure GPIO_89 as PAD_NC	Furquan Shaikh
2020-08-06	mb/google/zork: Add touchscreen power control	Furquan Shaikh
2020-08-06	mb/google/zork: Switch USI_RESET to active low polarity for v3.6+	Furquan Shaikh
2020-08-06	mb/google/zork: Use dev_nested_path for dmic gpio update	Josie Nordrum
2020-08-06	mb/google/zork: Make SW changes for HP_INT_ODL in schematic v3.6	Josie Nordrum
2020-08-06	mb/google/zork: Add kconfigs to check schematic version 3.6	Josie Nordrum
2020-08-06	mb/google/volteer: add support for ddr4 memory	Nick Vaccaro
2020-08-06	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro
2020-08-06	mainboard/google/puff: Remove second temp sensor	Andrew McRae
2020-08-06	security/intel/txt: Avoid shifting by a negative value	John Zhao
2020-08-06	arch/x86/pirq_routing.c: Drop unneeded `continue`	Angel Pons
2020-08-06	nb/intel/sandybridge: Drop inexistent device from DMAR	Angel Pons
2020-08-06	nb/intel/sandybridge: Deduplicate PCIEXBAR decoding	Angel Pons
2020-08-06	nb/intel/sandybridge: Refactor `get_pcie_bar`	Angel Pons
2020-08-06	drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable	Subrata Banik
2020-08-06	soc/intel/common/block/cpu: Refactor init_cpus function	Subrata Banik
2020-08-06	soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init	Huayang Duan
2020-08-06	mb/google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup	Huayang Duan