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2010-08-30Fix intel mtarvon compilation by switching it over to CAR.Stefan Reinauer
This should be unproblematic, as there are other boards with the same "socket" that work with CAR already. Tests are highly appreciated though! Acked-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Restructured all vendors' Kconfig files to no longer source the boards'Jens Rottmann
Kconfigs from within the choice/endchoice block. This makes it possible to define user visible board specific options. Moved all vendor names and PCI ids to the vendors' Kconfigs. Now all options in each file depend on the same symbol, so replaced all "depends on"s with a single "if". Sorted boards (sort -d), cleaned whitespace. This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is always "y" and never used. It it simply needed to have something to attach the boards' "select" statements to. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30This file was missing from r5751.Andreas Schultz
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Support for Lanner EM-8510 BoardAndreas Schultz
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> --- src/mainboard/Kconfig | 8 ++ src/mainboard/lanner/Kconfig | 8 ++ src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++ src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++ src/mainboard/lanner/em8510/chip.h | 23 +++++++ src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++ src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++ src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++ src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++ src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++ 10 files changed, 418 insertions(+), 0 deletions(-) create mode 100644 src/mainboard/lanner/Kconfig create mode 100644 src/mainboard/lanner/em8510/Kconfig create mode 100644 src/mainboard/lanner/em8510/Makefile.inc create mode 100644 src/mainboard/lanner/em8510/chip.h create mode 100644 src/mainboard/lanner/em8510/cmos.layout create mode 100644 src/mainboard/lanner/em8510/devicetree.cb create mode 100644 src/mainboard/lanner/em8510/irq_tables.c create mode 100644 src/mainboard/lanner/em8510/mainboard.c create mode 100644 src/mainboard/lanner/em8510/romstage.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Rework i855GM/i855GME supportAndreas Schultz
Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> --- src/northbridge/intel/i855/Kconfig | 30 + src/northbridge/intel/i855/i855.h | 76 +++ src/northbridge/intel/i855/northbridge.c | 21 + src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++----- src/northbridge/intel/i855/raminit.h | 14 +- 5 files changed, 1002 insertions(+), 175 deletions(-) create mode 100644 src/northbridge/intel/i855/i855.h git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30mPGA479M Sockets can take Intel Mobile Celeron.Andreas Schultz
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket. Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> This patch likely breaks the following two boards since it unconditionally activates CAR code for this socket: * digitallogic/adl855pc * intel/mtarvon stepan suggests moving those two boards over to CAR, too, so we don't have to worry. --- src/cpu/intel/socket_mPGA479M/Kconfig | 1 + src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+), 0 deletions(-) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Multi-DIMMS on AMD ddr2 MCT channel B fixed.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Multi-DIMMS on AMD ddr3 MCT channel B works.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30Trivial syntax correction of AMD mct_ddr3 dir.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Kerry She <Kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27drop three unneeded config variables:Jens Rottmann
- HAVE_HIGH_TABLES - HAVE_LOW_TABLES - FALLBACK_SIZE Jens Rottmann sent an almost identical patch at the same time, so Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26Remove unused mainboard_config definitions. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /Jens Rottmann
chipset support it. But this involves a long list of 'depends', which you have to remember updating manually. Converted this into HAVE_... properties, which will be inherited automatically if someone copies a chipset to create a new one. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26One of my boards needs this mini delay in order to survive ram initialization.Stefan Reinauer
Odd. The others don't. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26kontron 986lcd-m: Fix compilation if there is no oprom execution at all...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-25Fix i945 based boardsStefan Reinauer
- prevent GCC from inlining do_ram_command - it will break RAM initialization. - fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not 200us - move PCIRST# as early as possible (before ich7_enable_lpc) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-24* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.Aurelien Guillaume
* DRAM initialization done message is now printed in debug-mode only, rather than everytime. Signed-off-by: Aurelien Guillaume <aurelien@iwi.me> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-23mark unused variables in x86emu as unused. gcc has a mechanism for this.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22Fix up some copyrightsWang Qing Pei
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22I've checked Revision Guide for AMD Family10h processors (#41322) revXavi Drudis Ferran
3.74 June 2010 for errata 351 and it agrees with the comment on setting ForceFullT0= 000b but I believe the code didn't honor the comment. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22RB_C3 should also apply the workaround for errata 354, according toXavi Drudis Ferran
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22RB_C3 and HY-D0 should also apply the workaround for errata 344, according toXavi Drudis Ferran
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 My processor wasn't getting the workaround Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22documented workaround erratum 414, seeXavi Drudis Ferran
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 with patch.erratum414 it stops here (next patches don't make it get further, but they're needed according to documentation, don't break anything for me and I still don't have a solution for booting, so I'm keeping them there in case they fix something. testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading stage image. Check CBFS header at fffffd2e magic is 4f524243 Found CBFS header at fffffd2e Check fallback/romstage CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @ 0x20000 Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22documented workaround erratum 372, seeXavi Drudis Ferran
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010 with this one it stops here or earlier (as soon as before the patch, sometimes): *** Yes, the copy/decompress is taking a while, FIXME! v_esp=000cbf48 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22Complete code for errata 343. Revision Guide for AMD Family10hXavi Drudis Ferran
processors (#41322) rev 3.74 June 2010 says to set the register to 1 before CAR and to 0 after. We were setting it to 0 after CAR, but not to 1 before. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22Include RB_C3 in erratum 346Xavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.Xavi Drudis Ferran
While reviewing impact of this change it seems code for erratum 531 was not in sync with current docs. I have checked uses of AMD_FAM10_ALL, but I haven't looked up the docs for all of them, at first sight it seems ok to include all FAM10 revisions in this mask. Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010. Before it was applied also to DR-B0, DA-C3 or HY-D0 which are not affected according to current docs. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-20Remove a couple of warnings. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-20Add support for the HP DL145 G1, based on the Tyan s2881.Oskar Enoksson
Signed-off-by: Oskar Enoksson <oskeno@foi.se> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-18The attached file add pa78vm5 dev3 detection function to avoid the building ↵Wang Qing Pei
error. Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc ↵Rudolf Marek
needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and I removed the gpio asserts - I think those are not used here. The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better. The classic PCI slot works fine too. However it seems SATA has some issues. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Correct for size_t would be %zx, but coreboot's printf doesn't support this.Jens Rottmann
Trying to keep it simple: Two sizes are expected equal so use same %x for both. Cast to unsigned int to make sure it fits. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Commit (non-working!) Jetway PA78VM5 mainboard Wang Qing Pei
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Support for Fintek F71863FG. This might need some work on the copyrightWang Qing Pei
notices. Getting it into the tree so people can get to it. Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Another AMD 780/700 mainboard: Gigabyte MA78GM-US2HWang Qing Pei
http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov the simple config is AM2+DDR2+SB700+RS780, the superIO is IT8718F The patch has been tested with SeaBIOS + SUSE11.2 Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Tilapila supports both dual slot and single slot. The difference should beWang Qing Pei
detected by the existence of dev3. Some other RS780 mainboard has the same function. The patch added the function to make these boards work smoothly. Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Add support for Gigabyte MA785GMT mainboard.Wang Qing Pei
Details of the hardware configuration can be found at http://www.gigabyte.com/products/product-page.aspx?pid=3478 Brief configuration is: 1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor 2. North Bridge: AMD 785G 3. South Bridge: AMD SB710 4: Super IO : ITE8718F The mainboard has two bios flashchip. Coreboot ROM should be flashed into the M_BIOS (which means main bios). Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17fix nokia ip530 Kconfig, missed on last check-inStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Whatever happened here,... The DEC Tulip is a network card, no bridge of anyStefan Reinauer
kind. Move it to drivers and make the necessary adaptions. Also drop empty drivers/generic/generic and start cleaning up Makefiles in drivers/ Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Clarify comment a bitPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Look for actual framebuffer size instead of hardcoding UMARudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Fix warnings (that become errors) in AMDHT for certain configurations ↵Xavi Drudis Ferran
(unused functions) Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17Feature of lane reversal of AMD RS780 is tested.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-16White space changes for s2881 device tree.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-16Call mainboard init functions.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-15Gigabyte dual bios mainboard will always reboot, caused by the superio. Wang Qing Pei
After lots of testing, the SuperIO LDN 7, register 0xEF is the key to the problem. This patch adds a function which stops dual bios mainboards from rebooting, when called. Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-14My forgotten CAR cleanup patch...Stefan Reinauer
- Drop lots of dead code from the various cache_as_ram.inc files. - Use some descriptive macros instead of magic numbers for MTRR MSRs - drop unused duplicate descriptors from romstage GDT - slightly reformatting code and comments Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-14My old mcp55 azalia fix from May 2010. Was never checked in.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-14bootblock_prologue.c (not a .c file!) and i386/init/crt0_prologue.inc wereStefan Reinauer
pretty much 1:1 the same file (despite an include and a typo) so drop one instance of it. We only have one prologue.inc for the romstage code now. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-14clean up comment in entry32.incStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-13Build 8151 for s2885. Trivial.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 22:35:12 +0000