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2018-03-05mb/google/poppy: Allow use of optional secondary SPDFurquan Shaikh
This change adds support for variants to use secondary SPD if required. This enables a variant to have different types of memory supported using the same image. BUG=b:73514687 Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05mb/google/poppy/variants: Set pch_trip_temp to 75CFurquan Shaikh
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-05cpu/x86/mp_init: Increase AP check-in time-out to 1secondFurquan Shaikh
Currently, the AP check-in time-out in bsp_do_flight_plan is set to 100ms. However, as the number of APs increases, contention could increase especially for resource like UART. This led to MP record time-out issues on KBL platform with 7 APs and serial-console enabled BIOS image. This change increases the time-out value to 1 second to be on the safer side and let APs check-in before continuing boot. BUG=b:74085891 TEST=Verified that MP record time-out is not observed anymore on Nami. Change-Id: I979c11a10e6888aef0f71b5632ea803a67bbb0ff Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05soc/intel/common/block/smm: Add configurable delay before entering S5Furquan Shaikh
This change adds a configurable delay in milliseconds before SLP_EN is set in SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power button SMIs. On some platforms (Nami, Nautilus), it was observed that power button SMI triggered by EC was competing with the SLP SMI triggered by keyboard driver. Keyboard driver indicated power button press which resulted in depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power button press also causes the EC to send a pulse on PWRBTN# line, which is debounced for 16ms before an interrupt is triggered. This interrupt was generated after SLP_SMI is processed which resulted in the device waking back up from S5. This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay before SLP_EN is set for S5. This change should only affect CHROMEOS boards as the config option will be 0 in other cases. BUG=b:74083107 TEST=Verified that nami, nautilus do not wake back from S5 on power button press at dev mode screen. Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05lib: Add delay.c to smmFurquan Shaikh
BUG=b:74083107 Change-Id: I98ab5c84268e8754fbaf6a30cd26fe1084e45a20 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-03nb/intel/i945/gma: Log configured VGA modePaul Menzel
This is useful information, when debugging problems related to graphics. Change-Id: Iacb0ae5f012207192379fd07e91f4687ec32cdfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/23807 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02sb/intel/common: Fix conflicting OIC register definitionNico Huber
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-02console: only allow console messages after initializationAaron Durbin
The console subsystem allows printk() to be called prior to the drivers and/or infrastructure is completely set up. In those situations don't allow messages to be added until the console is completely initialized. BUG=b:73898539 Change-Id: Idc3840132d7f95f8e22045d7484c528d828bb0de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/24917 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02mb/google/zoombini/variants/meowth: Enable NVMeBora Guvendik
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3. BUG=b:72120814 TEST: Boot to OS via NVMe Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/23208 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02mb/hp: Enable additional ports at WWAN slot for ElitebooksIru Cai
2760p: enable PCIe 8470p: enable mSATA 8460p: enable PCIe, also add comments according to circuit diagram 2570p: comment for some USB ports Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-02ec/google/chromeec: Add note before error messageMartin Roth
When clearing events from the EC, an error is returned when we try to clear an event that doesn't exist. This is normal, but can be distracting when trying to track down an error, so add a message saying that the error is expected. BUG=None Test=Build Grunt with SMM debug enabled. See message before "EC returned error result code 1". Change-Id: Ib2e684e357e821c795de4b59658432c91a8d63fc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/24914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-02mainboard/google/zoombini/variant/meowth: enable speed shiftNick Vaccaro
BUG=b:73817825,b:69011806 BRANCH=master TEST=Build and flash to meowth, verify cpufreq shows up in kernel for all cores : localhost ~ # find / -name "cpufreq" /sys/devices/system/cpu/cpu3/cpufreq /sys/devices/system/cpu/cpu1/cpufreq /sys/devices/system/cpu/cpufreq /sys/devices/system/cpu/cpu2/cpufreq /sys/devices/system/cpu/cpu0/cpufreq /sys/module/cpufreq /usr/share/laptop-mode-tools/modules/cpufreq Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/24902 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/reef/sand: Override USB2 phy settingsKatherine Hsieh
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-sand coreboot chromeos-bootimage Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/23879 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01soc/intel/broadwell: Generate ACPI DMAR tableMatt DeVillier
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01soc/intel/broadwell: Enable VT-d and X2APICMatt DeVillier
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01mainboard/google/meowth: Turn on DBC over USB3.0Lijian Zhao
Intel DCI (direct connect interface) allows debug Intel target using USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0 only. BUG=None TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot image. Using DAL to halt/run CPU. Change-Id: I39e68dabfcb9e659733019334299e562eee3681d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-03-01mb/google/poppy/variant/nautilus: Change SlowSlewRateForSa settingSeunghwan Kim
If switch to VT2 on nautilus, screen flicker appears. We found if we rollback the change of slew rate setting, then the flicker issue will be gone: https://review.coreboot.org/c/coreboot/+/22588 But nautilus board needs slew rate tuning to reduce EE noise, so we decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of rollback the whole change of the CL:22588. It can remove the flicker on VT2. BUG=b:71397040 BRANCH=master TEST=emerge-nautilus coreboot Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/23877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-01mb/google/reef: Override USB2 phy settingsTim Chen
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/23878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/coral: add usb2 phy setting override for some variantsSheng-Liang Pan
Due to there are some chances USB devices can not be detected. USB2 port#1 and #4 PHY register need to be overridden for variants Santa/Lava/Blue/Bruce/Astronaut. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I401905685cc3078df657919b162272c3de320296 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/23881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-01mb/{amd/gardenia,google/kahlee}: Initialize GPIOs earlierJustin TerAvest
The GPIOs for PCIe reset and power enable for WLAN must be set up before amdinitearly for wlan to function. BUG=b:73898539 TEST=Boot, see WLAN controller in lspci Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24916 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01soc/amd/stoneyridge: Remove printk for GPIOJustin TerAvest
The printk() calls in sb_program_gpios() aren't necessary, and incur a 13 second delay if the function is called from bootblock_mainboard_early_init(). This commit removes them so GPIOs can be set up earlier. TEST=call sb_program_gpios from bootblock_mainboard_early_init BUG=b:73898539 Change-Id: I064291decf47d86132e36469e029b3262ec20172 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24915 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/scaleway/tagada: set SMBIOS Enclosure Type in KconfigJulien Viard de Galbert
Change-Id: I7acffcf3fc36742c77ce00b253f5b0a68d435798 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24911 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01smbios: Add option to select the enclosure typeJulien Viard de Galbert
This allows for a mainboard to change the value from its Kconfig. The default value is still SMBIOS_ENCLOSURE_DESKTOP (0x03) or SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set. Change-Id: I35bc913af69565531831746040a0afe0cabe1c58 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-28drivers/intel/fsp2_0: Fix build error while DISPLAY_HOBS is selectedSubrata Banik
This patch fixes brokenness issues in coreboot with CONFIG_DISPLAY_HOBs config selection due to recent UDK2017 package changes. TEST=Build and boot UDK2017 platforms with DISPLAY_HOBS select. Change-Id: I5c779c86870c62253d64c6af456bf017553e269c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mainboard/google/zoombini: consolidate SPD makefilesNick Vaccaro
- consolidate commonality in meowth and zoombini's SPD makefiles into a common zoombini/spd/Makefile.inc - move all SPD hex files into zoombini/spd directory - move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc BUG=b:69011806,b:71776625 BRANCH=master TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot' compile and boot successfully. Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23874 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28skylake: Fix unwanted disablement of ACPI UPWEKane Chen
In PORTSC, Port Enabled/Disabled(PED) is RW1CS. When there is a USB device attached on system, current UPWE method will set 1 to PED, this will cause port disabled as it's RW1CS. This change is inspired by xhci_port_state_to_neutral in linux driver. It will mask all RO and RWS bits and set WDE and WCE. BUG=b:70777816 TEST=System won't be awakend from s3 automatically when usb devices is attached. Also system can be awakend by hotplugging usb devices under S3. Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mb/google/poppy/variants/nami: Enable elan touchscreenCrystal Lin
BUG=b:72062694 BRANCH=master TEST=Verify touchscreen on nami works with this change. Change-Id: Iaec71a11121b3d2849f12d18cda0e506be2ace09 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/23872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28mb/google/octopus: Add LPDDR4 memory initRavi Sarawadi
Add LPDDR4 initialization support. BUG=b:73136980 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ieffcfa2f9d075eb0be13562f1a0c7ee503b005d9 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-28soc/intel/skylake: Add support to print ME versionFurquan Shaikh
This change adds a boot state callback to print ME version after DEV_ENABLE is complete. Information is printed only if UART_DEBUG is enabled because talking to ME to get the firmware version adds ~1 second to boot time. TEST=Verified on Soraka that ME version printed is correct. Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-27sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common locationArthur Heymans
Many generations of Intel hardware have identical code concerning the RCBA. Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-26soc/amd/stoneyridge: Refactor northbridge resource allocatorMarc Jones
The resource allocator was overly complicated due to porting from a multi-node resource allocator. It had some assumptions about the UMA memory and where it would be located. The refactored allocations account for UMA being reserved above 4GiB. TEST=Check CBMEM table has correct RAM regions. Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common: Save the UMA settings from AGESAMarc Jones
Save the UMA base and size settings returned by AGESA in amdinitpost(); Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26mainboard/google/zoombini: enable 4 coresNick Vaccaro
BUG=b:70731385 BRANCH=master TEST='emerge-meowth coreboot chromeos-bootimage', flash image.serial.bin to meowth board, boot into kernel, and verify 4 cores are running. Change-Id: Ia233e41acd19b317f82433a5d41d84ea934a66c4 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23839 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26src/arch/x86/smbios.c: Fix type 17 part numberRichard Spiegel
Some DIMMs have invalid strings when it comes to device part number (bytes 0x149-0x15c). From DDR4 SPD specs it should be ASCIIZ with unused space filled with white spaces (ASCII 0x20). Byte 20 should be 0 (ASCIIZ), all others should be ASCII. Create a test that detects invalid strings and replace invalid characters with *. If a replacement was made the output string then must be <Invalid (replaced string)>. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Use code to examine SMBIOS, while testing different valid and invalid strings. Remove string injection before committing. Change-Id: Iead2a4cb14ff28d263d7214111b637e62ebd2921 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common/block/pi/amd_late_init.c: Fix part numberRichard Spiegel
Kahlee DIMM have invalid string when it comes to part number (bytes 0x149-0x15c). We currently force a NA string, but grunt has the proper strings. Just let the string go through, and a second commit within smbios.c will be responsible for testing the string and taking proper action. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Remove string injection before committing. Change-Id: I427262873f9ec80f459245e5f509e28a68de3074 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26ec/google/chromeec: Remove extra newline characters from printkFurquan Shaikh
This change removes extra newline characters from print statements for wake masks. Change-Id: I13cde76bfb0f10b1dda8117c27f2891e909f9669 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-26mb/siemens/mc_bdx1: Avoid dereferencing a NULL pointerWerner Zeh
Coverity scan has found an error where a NULL pointer is dereferenced. The bug would happen if the devicetree does not contain a valid entry for PCA9538. In this case the code * if (dev->path.i2c.device == PCA9538_SLAVE_ADR) would dereference to a NULL pointer. This patch fixes this issue. Thanks coverity! Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL)) Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-23mb/google/fizz: Enable PCIe port 11, 12Zhongze Hu
Our CFM daughter card would like to use individual PCIe lanes for two different devices on the card. dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b connector on fizz to meet the requirement: https://chrome-internal-review.googlesource.com/571936 We also need to enable the ports on device tree. BUG=b:72523836 TEST=none BRANCH=fizz Change-Id: Icded9850d833752680e0174b6c476e657817b319 Reviewed-on: https://chromium-review.googlesource.com/923867 Commit-Ready: Zhongze Hu <frankhu@google.com> Tested-by: Zhongze Hu <frankhu@google.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924860 Commit-Queue: Shelley Chen <shchen@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/23845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-02-23console: Introduce a way for mainboard to override the loglevelJulien Viard de Galbert
This change adds a config option to allow mainboard to override the console loglevel. When the option is set, the platform has to define the function get_console_loglevel returning a valid loglevel value. This allows a mainboard to sample a GPIO to switch the loglevel value between different environments (qualification vs production) without re-flashing. Change-Id: Id6cc72b8fe5c4c50a6f83ce80e6440b078eec6e2 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-22mb/google/kahlee/mainboard.c: Fix mainboard_picr_dataRichard Spiegel
While programming interrupts, a message "perhaps this device was defined wrong?" shows up twice. This is caused because some devices have interrupt programmed for APIC mode, but not for non-APIC mode. Fix mainboard_picr_data table by identifying devices programmed with value 0x1F while programmed differently on mainboard_intr_data table. Do so only for devices that are used by kahlee or interrupt required by old OS. BUG=b:70788755 TEST=Build and run kahlee, Verify that message disappears from serial output. Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22mb/google/kahlee: Use GPIO macros for baseboardJustin TerAvest
This commit uses newly defined macros to make it easier to read which iomux function pads are being configured to use. TEST=Booted grunt, confirmed display backlight came on. BUG=b:72875858 Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22soc/amd/stoneyridge: Add readable macros for GPIOJustin TerAvest
This commit defines a set of macros for defining GPIO configuration that are easier to read than the raw iomux function values used today. TEST=None BUG=b:72875858 Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22mb/google/kahlee: Correct bad gpio entryJustin TerAvest
There's no need to set the output enable here; this is already handled by the native function. I'm making this correction in this change to prevent the GPIO pin descriptions from getting confusing. BUG=b:72875858 TEST=Booted, confirmed S5_MUX_CTRL high with and without this change. Change-Id: I9e047be7169586c59892ef2bdab915683feeebda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mainboard/google/meowth: enable PCH iSCLKLijian Zhao
Turn on PCH iSCLK for meowth platform. BUG=None TEST=Boot up into OS and check register programming with iotools, the command is iotools mmio_read32 0xfdad8000, returned value is 0x03. Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23368 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22device/ddr2,ddr3: Rename and move a few thingsArthur Heymans
In order for ddr2.h and ddr3.h to be included in the same file it cannot have conflicting definitions, therefore rename a few things and move some things to a common header. Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-02-22mainboard/google: Disable big, pit, and ryu ec buildsMartin Roth
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed from the latest EC codebase, so don't try to build them by default anymore. Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao
Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. BUG=b.71586766 TEST=Install OS into EMMC successfully on meowth P1 platform. Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22soc/intel/cannonlake: Add emmc/sdc port idLijian Zhao
EMMC and SD Controller port id listed here, the port id definition came from Cannonlake BIOS Writer Guide 570374. BUG=None TEST=None Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22mainboard/google/zoombini: Add config for meowth audioSathyanarayana Nujella
Add NHLT and dt support for meowth with max98373 amp. BUG=b:71724897 TEST='emerge-meowth coreboot' compiles correctly TEST=check SSDT and verify entries for max98373 TEST=check NHLT ACPI tables included blobs for max98373 Change-Id: Ic89bf669c7ab2ef39ce64e4da6a57a7069ee75f9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-22soc/intel/cannonlake: Add more HDA Audio Link settingsLijian Zhao
Since FSP version 7.x.11.43, more HDA Audio link options are exposed, so included that into coreboot. Users can modify that base on platform implementations. BUG=None TEST=Boot up with debug build version FSP and check the debug print result on meowth platform. Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 18:58:08 +0000