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2019-01-14soc/intel/apollolake: Add option to disable xHCI Link Compliance ModeJohn Zhao
Provide options to disable xHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. BRANCH=octopus BUG=b:115699781 TEST=Verified booting to kernel. Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30816 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/google/hatch: Use USB2 Port 10 for BT over CnViAamir Bohra
Integrated BT controller in CnVi uses USB port 10 for communication. BUG=b:122552619 TEST=lsusb shows BT device Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30809 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14mb/lenovo/[xtz]60: Introduce and use RCBA64 macroPeter Lemenkov
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14mb/lenovo/*/romstage: Use macros instead of magic numbersPeter Lemenkov
Apparently coreboot still uses magic numbers instead of macros in some Lenovo mainboards. Let's use macros instead. Note that IOTR[0123] is a 64-bit width variable. Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14sb/intel: Use common RCBA MACROsPeter Lemenkov
This commit follows up on commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-14soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()Patrick Rudolph
Move early_mainboard_romstage_entry before console_init. Allows to setup a SuperIO, if any, for serial console. Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14intel/fsp1_0: Add option to select FSP debug levelPatrick Rudolph
Useful for debugging FSP. Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-14soc/intel/fsp_broadwell_de: Fix uartPatrick Rudolph
* Disable FSP serial output if not CONSOLE_SERIAL Tested on wedge100s. Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14AGESA binaryPI: Consolidate ACPI for IMCKyösti Mälkki
Change-Id: Ieff6041f3c9ad02f9cebae0ec83d0898abb0d601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14AGESA binaryPI: Remove unused IMC ACPI methods IMSP and IMWKKyösti Mälkki
Note that IMC must sleep while SPI writes are in progress. Instead of using these ACPI methods, flashrom currently does raw IO to achieve the same. Change-Id: Ifca4e8328c54d1074b4799ddecfece24607214db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18537 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14binaryPI: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: I6a58ab53d4a800d4c0c2026e50826122ece2c59f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-01-14AGESA: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-14AGESA/PI: replace HUDSON_DISABLE_IMC with HUDSON_IMC_ENABLEMike Banon
Only a few boards are using IMC for the onboard fan control, so regarding the availability of IMC selection it should be opt-in, not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2 because Gizmo 2 could use IMC for the onboard fan control. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16 Reviewed-on: https://review.coreboot.org/c/30756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14drivers/spi/amic.c: Add the rest of >=1MB AMIC A25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic5bd3e43e0d3fd5f454fae71b307c0682f203d5c Reviewed-on: https://review.coreboot.org/c/30884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14drivers/spi/adesto.c: Add the rest of >=1MB Adesto AT25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I8c0e6d8f1487ca90f88d4a56af3fb0e21458ef1e Reviewed-on: https://review.coreboot.org/c/30883 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14drivers/spi/gigadevice.c: Add the rest of >=1MB Gigadevice GD25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I333c8589ddc2bece488608ff66015ca8307eae0f Reviewed-on: https://review.coreboot.org/c/30882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14drivers/spi/macronix.c: Add the rest of >=1MB Macronix MX25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I4508a65a5bdcbf58aadf452de5e896fc3c5b1bc3 Reviewed-on: https://review.coreboot.org/c/30877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14drivers/spi/spansion.c: Add more Spansion S25FL_K chipsMike Banon
Add S25FL208K (ID 0x4014), S25FL132K (ID 0x4016) and S25FL164K (ID 0x4017) chips in a way similar to S25FL116K (ID 0x4015) chip from the same family. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7 Reviewed-on: https://review.coreboot.org/c/30874 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13google/butterfly: correct northbridge selectionMatt DeVillier
butterfly is a Sandybridge device, and selecting Ivybridge breaks libgfxinit currently due to CPU mismatch Test: build/boot butterfly w/libgfxinit Change-Id: I1a7f5a3681d21a256834b11b545855c4365f5f78 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30820 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13google/butterfly: add cpu/gpu pwm backlight register valuesMatt DeVillier
Required for functional internal display on butterfly using libgfxinit. Test: boot/build butterfly, verify internal display functional prior to OS driver loading. Change-Id: Ib8060f2d1ad0694f0886d35c83763907f61b47b1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30819 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()Elyes HAOUAS
Use hexdump() instead of dump_mem(). Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13nb/intel/x4x: Remove spurious pcidev_on_root() usageNico Huber
It's supposed to be the same device that is passed to the executing function. Change-Id: I6cf994390c16e0393c96a2b2e04a36305be88e68 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13nb/intel/i945: Reduce pcidev_on_root() callsNico Huber
Also removes one call for 0:2.0 (integrated graphics) that might be disabled. Change-Id: I494aa366030b77baf431f29ba331f13f7c567025 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13sb/intel: Check for NULL-return of pcidev_on_root()Nico Huber
In these cases we have to expect a NULL pointer because the IGD device 0:2.0 may be disabled. The behaviour still differs from using dev_find_slot(), which may return a disabled device. Though, if you'd try to read its config space you'd only read garbage (0xff) and in cases where we filled ACPI data with devicetree information, the information shouldn't be interpreted by the OS because of the disabled device. Change-Id: I1bab8fa3a82daca71d03453315cdd69d8951fc24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30879 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13usbdebug: Remove option DEBUG_USBDEBUGKyösti Mälkki
Superseeded with DEBUG_CONSOLE_INIT. For dbgp_print_data() return early and skip reading registers when dprintk() would not get printed anyways. Change-Id: Idf470b8572ad992c8d4684a860412d9140f514ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-13console: Add Kconfig debug option DEBUG_CONSOLE_INITKyösti Mälkki
Under normal circumstances no printk() goes through until console_hw_init() has completed. This is wanted behaviour, except when you need to debug the setup of one of consoles. Change-Id: Ifc2bb22bf930009ee229d4461f512ada3018307b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-13mb/google/kukui: add flapjack on top of kukuiYH Lin
Add placeholder for future flapjack additions/modifications. BUG=None BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ib9cd39e284f19b9179da73ed9f2b13d97442960e Reviewed-on: https://review.coreboot.org/c/30859 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki
This board is the only user of these ancient chipsets, so we'll do all in one go. Also wipe out some extra headers. Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-13arch/x86: Drop Kconfig AP_SIPI_VECTORKyösti Mälkki
This was used to check romcc-built bootblock and romstage agree about the location of 16-bit entrypoint. There was no need to customize it as bootblock size requirement did not grow. Just check for a fixed location at 4 GiB - 4 KiB. With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol for the purpose, since it appears in the same compilation unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes. Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-13cpu/intel/car/p4: Update microcode in CAR setupArthur Heymans
This updates the BSP microcode during CAR setup. Change-Id: I87d34cf38dbd700ecb04d87c5b4767910e4a922c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30682 Reviewed-on: https://review.coreboot.org/c/30777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-12soc/intel/cannonlake: Hook up MicrocodeLijian Zhao
Hook Coffeelake U43e and Coffeelake H/S/E3 microcode into SOC and remove the MICROCODE_BLOB_NOT_HOOKED_UP. BUG=N/A TEST=Boot up with coffeelake rvp board and check microcode revision in coreboot log. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I6593081374dd4898a82db5b43c3b5bf154b3ef60 Reviewed-on: https://review.coreboot.org/c/30864 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-11src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260Gaggery Tsai
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS is by default GEN1 and ThP has bad synchronization on polarity inversion. When the root port request for speed change, ThP doesn’t confirm the request, and both sides are moving to polling after timeout, hot reset is issued, and then most of the CFG space is initialized. From the observation, CCC/ECPM/LTR would be reset to default but CCC/ECPM of root port and end devices have been reconfigured in pci_scan. The LTR configuration for root port is still missing. BUG=B:117618636 BRANCH=None TEST=Warm/cold reset for 10 times and didn't see unsupported request related AER error messages & $lspci -vvs 00:1c.0|grep LTR and ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68 and ensure bit10 is set. Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/30486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer
With the commit a96e66a (soc/intel: Clean mess around UART_DEBUG), an adjustment is necessary for this mainboard. Change-Id: I0fb6288959f8bcb45c4cc93cc132f31a5ab2a5ad Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/30836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11Revert "cpu/amd: Use `get_option()`"Paul Menzel
This reverts commit 6fffd70435084fb1d3237fcb1a11f11849721e8f. Doing more tests on the Asus KGPE-D16, it seems to cause a reboot loop quite often. Therefore, revert the commit. The problem might be caused by the spinlocks used by `get_option()`, and which are not used by `read_option()`. Change-Id: Ic25129aa71c8e8e40a65bb2658de78005766fea8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11console/Kconfig: Fix dependency of FIXED_UART_FOR_CONSOLENico Huber
The Kconfig declaration for FIXED_UART_FOR_CONSOLE was accidentally placed inside an `if CONSOLE_SERIAL` in a96e66a (soc/intel: Clean mess around UART_DEBUG). TEST=Start a clean config, select intel/leafhill and disable serial console. Confirm that config can be saved without error. Change-Id: Ie41687e91af11a13697cbe25938dada2c74b40fb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11arch/x86/ebda: Don't trash the EBDA on the resume pathArthur Heymans
Clearing the EBDA was introduced with b4aaaa "Prepare the BIOS data areas before device init." which states that the purpose of setting up these area's is just to make sure they are sane. On the S3 path doing this is not needed and can even thrash data set up by payloads (mostly SeaBIOS) that used that memory. Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11cpu/intel/microcode: Support update before CAR entryArthur Heymans
Change-Id: Ie3c2d2e1bc79dcaffd9901e17f83ceeaabd1d659 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11arch/x86/lapic: Remove second stack poisoningKyösti Mälkki
It was already done once in c_start.S. Change-Id: I1cb0ea25251644dbd1127d177247a02ba52bb550 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-10mainboard/google/octopus: configure EC_AP_INT_ODLJett Rink
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards that support it. Also removing unnecessary IO standby support since we don't use this pin to wake up the SoC. BRANCH=octopus BUG=b:122552125,b:120679547 TEST=CTS tests with changes Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30788 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10soc/intel/fsp_broadwell_de: Drop MICROCODE_BLOB_NOT_HOOKED_UPNico Huber
It's been hooked up in the meantime. Change-Id: I64176b09e375034189000ea4308c58771f0019a1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/30812 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10northbridge/amdfam10: Deal with PCI_ADDR() betterKyösti Mälkki
PCI_ADDR() is tightly coupled with different setup_resource_map() variants so move the declaration away from global namespace. In the implementation of setup_resource_map() use the bottom 12 bits as the register mask like the other variants do already. Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30784 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10amdfam10 boards: Simplify early resourcemapKyösti Mälkki
Purpose of the table is to load initial address maps on PCI function 0:18.1. Provide a macro of its own so it is clear no other PCI devfn is accessed here. Change-Id: Ic146207580a5625c4f6799693157b02422bef00a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10sb/nvidia/mcp55: Avoid confusion with PCI_ADDR()Kyösti Mälkki
What you see in the table are not the PCI devices that will be written to. Use a helper MCP55_DEV() to make you look twice what is actually done. Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10sb/nvidia/ck804: Avoid confusion with PCI_ADDR()Kyösti Mälkki
What you see in the table are not the PCI devices that will be written to. Use a helper CK804_DEV() to make you look twice what is actually done. Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10amdfam10 boards: Drop extern on apicid_sp5100Kyösti Mälkki
The value get_bus_conf() initialises this value to is discarded. Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TOPatrick Georgi
TCO2_STS_SECOND_TO was renamed to TCO_STS_SECOND_TO but one use slipped through. Change-Id: I9e3b1cc5cb2f319db35416edf6cea612d755d40a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30805 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10device/pci_device: Do not break tree topologyKyösti Mälkki
Fix regression introduced with commit ad7674e device: Introduce pcidev_on_root() and friends Function pci_scan_bus() breaks bus->children link in the devicetree topology while scanning a bus. While the scan is in progress, accessing PCI devices with number higher than what is being probed was not possible because new pcidev_on_root() relies on having proper topology present at any time. Change-Id: I7bb497f7390628dd2f0310b380f199783a888c4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-10sb/intel/common: Show "Add EC firmware" only for boards that need itJan Tatje
Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to enable this option for boards that need it. The following list of boards requiring this was provided by Lijian Zhao: 1. intel/cannonlake_rvp 2. intel/coffeelake_rvp 3. intel/icelake_rvp 4. google/sarien 5. google/hatch Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik
This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 10:26:53 +0000