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2019-09-30device/i2c_bus: Add i2c_dev_read_at16()Nico Huber
i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger EEPROM parts), then reads bytes up to a given length into a buffer. Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30pci_ids: fix PCI ID for Intel Iris HALO GT4 iGPUMaxim Polyakov
According to the documentation [1], SKL-H Halo GT4E (Iris Pro Graphics P580) PCI ID should be 0x193B. [1] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM) Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference Manual. Volume 4: Configurations. May 2016, Revision 1.0 Doc Ref # IHD-OS-SKL-Vol 4-05.16 Change-Id: Id62fe3ec26779d51b748efd271db565ade1e3ee0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-30pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_HMaxim Polyakov
The new macro name contains the number of cores: PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core Change-Id: I190181b213d55865aa577ae5baff179fef95afde Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mediatek/mt8183: Init SPM driverDawei Chien
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200 Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-30soc/intel/skylake: Fix ACPI exception AE_NOT_FOUNDPatrick Rudolph
Make sure to match devices on the root bus only. This fixes an issue where the SoC returned "MCHC" as ACPI name for devices behind bridge devices, as the DEVFN matched. Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI path no longer contains invalid names. Tested on Supermicro X11SSH-TF. Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30mb/supermicro/x11-lga1151-series: x11ssh-tf: remove unneeded ACPI ifdefMichael Niewöhner
This removes the "ifdef ACPI" which is not needed here as we currently don't include gpio.h in any asl file. Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mb/supermicro/x11-lga1151-series: fix cmos layout and add default configMichael Niewöhner
This fixes the warning that power_on_after_fail could not be found, adds a default config and adds the parameter hyper_threading. Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35526 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30vboot: create board-specific test-only GBB HWID if not setHung-Te Lin
The HWID in vboot GBB is an identifier for machine model. On Chrome OS, that should be provisioned in manufacturing process (by collecting real hardware information), and will be checked in system startup. For bring up developers, they usually prefer to generate a test-only string for HWID. However that format was not well documented and cause problems. Further more, most Chromebooks are using HWID v3+ today while the test-only HWID is usually v2. Non-Chrome OS developers may also prefer their own format. To simplify development process, the GBB_CONFIG now defaults to empty string, and will be replaced by a board-specific test-only v2 HWID automatically. Developers can still override that in mainboard Kconfig if they prefer v3 or other arbitrary format. BUG=b:140067412 TEST=Built 'kukui' successfully. Removed kukui GBB config and built again, still seeing correct test HWID. Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30device,drivers/: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30getac/p470: Drop unused PCI secondary bus resetKyösti Mälkki
Change-Id: I959cdc08d43fea28f8bbc649cd46bab5656d6ca8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30console: Declare empty printk() for __ROMCC__Kyösti Mälkki
The typical do { } while (0) did not work, so provide empty stub function instead. Change-Id: Ieb0c33b082b4c4453d29d917f46561c0e672d09a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guardsKyösti Mälkki
Change in ssus_disable_internal_pull() is for romcc compatibility. Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-30mb/siemens/mc_bdx1: Enable VBOOTWerner Zeh
Enable VBOOT in Kconfig and provide a flashmap that includes all the needed sections for VBOOT support. Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30fsp_broadwell_de: Enable early write access to the SPI flashWerner Zeh
If VBOOT is used on a mainboard based on fsp_broadwell_de then VBOOT needs to be able to write to its NV data which may be stored on the SPI flash. Enable write access to the SPI flash on SoC level. If the mainboard does not use VBOOT the linker will drop the extra code. The benefit is that this code is at least compiled and therefore build tested with fsp_broadwell_de. Change-Id: I90a2d30f5749c75df2b286dce6779f10dde62632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30mb/google/drallion: Adjust GPD3 pin terminationBora Guvendik
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 section 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on drallion platform, able to boot up into OS and stay at power up state. Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-09-30mb/google/drallion: De-assert WWAN reset signalAamir Bohra
BUG=b:141734594 Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-29amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICEKyösti Mälkki
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29device/pnp_ops: Add ENV_PNP_SIMPLE_DEVICEKyösti Mälkki
Source files including this may have locally defined __SIMPLE_DEVICE__ so this cannot be placed in <rules.h>. Change-Id: I2336111b871203f1628c3c47027d4052c37899dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35653 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29device/pci_ops: Add ENV_PCI_SIMPLE_DEVICEKyösti Mälkki
Source files including this may have locally defined __SIMPLE_DEVICE__ so this cannot be placed in <rules.h>. Change-Id: If700dd10fd5e082568cd6866bfd802fc2e021806 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35652 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29intel/fsp_baytrail: Drop unnecessary lookup for PCI 0:0.0Kyösti Mälkki
It is safe to assume this to be copy-paste from eg. i945 where registers of said PCI device were read. Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki
The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-28cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ useKyösti Mälkki
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28usbdebug: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
We can always PCI config accessors with pci_devfn_t. Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28drivers/net/ne2k: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
Note that the code assumes mainboard code to configure any PCI bridges prior to calling console_init(). Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28arch/arm,mips: Use generic PCI MMCONFKyösti Mälkki
We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb/via/vx900: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: I840131f91e79c740c0c8784c252723ae90ded458 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28device/pci: Replace some __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb/intel/x4x: Avoid x4x.h header with romcc-bootblockKyösti Mälkki
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-28mb/google/variants/drallion: Update the spd index mapAamir Bohra
BUG=b:141575294 Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-28mb/google/drallion: Set UART for console to UART controller 0Aamir Bohra
Drallion uses UART 0 for console, change the config accordindly. BUG=b:139095062 Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28Kconfig: Hide CONFIG_CBFS_SIZE when an FMDFILE is providedArthur Heymans
CONFIG_CBFS_SIZE should only be used as a parameter to generate the default FMAP. This also swaps around FMDFILE and CBFS_SIZE to avoid that the CBFS_SIZE entry disappears when filling in the FMDFILE entry below it. One advantage is that if code references CONFIG_CBFS_SIZE the jenkins buildtest will most likely fail as many boards provide an FMD file. Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-28mb/lenovo/x131e: enable mSATA slotJames Ye
Per google/stout. Tested with SanDisk SSD U110. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-27mb/lenovo/x131e: correct USB port configJames Ye
Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-27fmap: Add get_fmap_flash_offset()Furquan Shaikh
CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. Since find_fmap_directory() is no longer used outside fmap.c, this change also removes it from fmap.h and limits scope to fmap.c. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-27device: add commentary to dev_find_slot()Aaron Durbin
dev_find_slot() can sometimes fail to return the desired device object prior to full PCI enumeration. Comment the declaration and implementation accordingly to help the user understand the problem and avoid its usage. Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27mb/supermicro/x11-lga1151-series: remove unneeded vendor id configMichael Niewöhner
The vendor id option set here is useless as most SSVID registers get filled with 0x8086 (their VID) by default, anyway. Besides that the Kconfig option isn't meant for retrofit ports, cf. commit 7e1c83e31bd (Add Kconfig options to override Subsystem Vendor and Device ID). The right place would be the devicetree. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: If67c679bb342f63096902535734106e4f1651118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-27lib/bootsplash: Fix compilationPatrick Rudolph
Add missing include. Tested on Supermicro X11SSH-TF. Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCKKyösti Mälkki
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-26soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id codeRichard Spiegel
All solid state devices have vendor id defined by JEDEC specification JEP106, which originally allocated only 7 bits for it plus parity. When number of vendors exploded beyond 126, a banking proposition came maintaining compatibility with older vendors while allowing for 4 extra bits (16 banks) through the introduction of the concept "Continuation code", denoted by the byte value of 0x7f. Examples: 0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o 0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2 BUG=b:141535133 TEST=Build and boot grunt. Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-26soc/intel/fsp_broadwell_de: move get_busno1() into vtd.cAndrey Petrov
TEST=just build it Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-26mb/supermicro: restructure x11ssh-tf to represent a x11 board seriesMichael Niewöhner
Most of the X11 boards with socket LGA1151 are basically the same boards with just some minor differences like different NICs (1 GbE, 10 GbE), number of NICs / PCIe ports etc. There are about 20 boards that can be added, if there is a community for testing. To be able to add more x11 boards easily like x11ssm (see CB:35427) this restructures the x11ssh tree to represent a "X11 LGA1151 series". There were multiple suggestions for the structure like grouping by series (x10, x11, x...), grouping by chipset or by cpu family. It turned out that there are some "X11 series" boards that are completely different. Grouping by chipset or cpu family suffers from the same problem. This is why finally we agreed on grouping by series and socket ("X11 LGA1151 series"). The structure uses the common baseboard scheme, while there is no "real" baseboard we know of. By checking images, comparing logs etc. we came to the conclusion that Supermicro does have some base layout which is only modified a bit for the different boards. X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we expect the other boards to have mostly the same device tree, there is a common devicetree that gets overridden by each variant's overridetree. Besides that some very minor modifications happened (formatting, fixing comments, ...) but not much. Documentation is reworked in CB:35547 Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26mb/mainboard/hatch: support elan touchpad for AkemiPeichao Wang
Modify IRQ pin from D21 to A21 and support wake-up from touchpad BUG=b:141519690 TEST=build bios and verify elan touchpad works fine Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26google/grunt: add new two DDR source for TreeyaPeichao Wang
new DDR particle: 1. Samung K4A8G165WC-BCWE 2. Hynix H5AN8G6NCJR-XNC BUG=b:139085024 BRANCH=master TEST=rework new source to DUT and re-flash bios to DUT and verify DUT will bring up successfully Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-26cpu/intel/: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-26cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
It is only called in ramstage. Even if it was called in romstage, execution flow is such that BSP and AP CPUs should not be able to enter update_microcode() routine concurrently. Also the Kconfig guarding the spin_lock() calls are not selected nor are the lock variables declared for these platforms. Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25soc/fsp_broadwell_de: fix flashconsole support for platformMatt DeVillier
CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert the changes back to usage of CAR_GLOBAL in the common spi driver so that flashconsole will work again in romsatge for fsp_broadwell_de. Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-25mb/google/kukui: Add new build target 'Juniper'Hung-Te Lin
Add the configuration 'Juniper' for the new mainboard. BUG=b:137517228 TEST=make menuconfig; select 'juniper' and build Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-25mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to KconfigFurquan Shaikh
All variants of hatch are using Comet Lake and so the selection can be done in Kconfig without requiring each variant to do the same. Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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