coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-10-23	soc/intel/cannonlake: Increase stack size from 4KiB to 8KiB	John Zhao
2017-10-23	mainboard/google/coral: Add USB2 phy setting override for Astronaut	ren kuo
2017-10-22	nb/intel/pineview: Port ACPI opregion to pineview	Patrick Rudolph
2017-10-22	superio/ite/common: Make PECI a thermal mode	Vagiz Trakhanov
2017-10-22	superio/ite/common: Add temperature limits	Vagiz Trakhanov
2017-10-22	superio/ite/common: Add temperature offset	Vagiz Trakhanov
2017-10-22	soc/intel/cannonlake: Change max root port to 16	Lijian Zhao
2017-10-22	security/vboot: Move vboot2 to security kconfig section	Philipp Deppenwiese
2017-10-22	soc/intel/skylake: pass SataSpeedLimit param to FSP2	Matt DeVillier
2017-10-22	purism/librem13v2: Update microcode length in CBFS	Youness Alaoui
2017-10-22	purism/librem13v2: Fix USB settings and set OC pin	Youness Alaoui
2017-10-22	purism/librem13v2: Update devicetree settings	Youness Alaoui
2017-10-22	purism/librem13v2: Change DRAM Rcomp/DQS values	Youness Alaoui
2017-10-22	purism/librem13v2: Add reading of serial number from CBFS	Youness Alaoui
2017-10-22	skylake/me: Add debug output of HFST registers	Youness Alaoui
2017-10-22	google/kahlee: Add PSP to devicetree.cb	Marshall Dawson
2017-10-22	amd/gardenia: Add PSP to devicetree.cb	Marshall Dawson
2017-10-22	soc/amd/common: Revert PI blob search hack	Marshall Dawson
2017-10-22	src/security: Add security kconfig stub	Philipp Deppenwiese
2017-10-22	mb/google/link: Enable libgfxinit	Nico Huber
2017-10-22	soc/amd/stoneyridge: Remove duplicate macros in pci_devs.h	Chris Ching
2017-10-22	intel/i210: Set bus master bit in command register	Werner Zeh
2017-10-20	kahlee: Set Kahlee GPEs	Marc Jones
2017-10-20	cr50_enable_update: Add printk before EC hibernate	Shelley Chen
2017-10-20	google/fizz: Set PL2 value based on sku id/charge max power	Shelley Chen
2017-10-20	chromeec: Add function to retrieve usb c charger info	Shelley Chen
2017-10-20	lib/gpio: constify array inputs	Aaron Durbin
2017-10-20	stoneyridge: Add SCI/GPE configuration	Marc Jones
2017-10-20	soc/stoneyridge: Remove _PRW ASL	Marc Jones
2017-10-20	stoneyridge: Fix USB ASL	Marc Jones
2017-10-20	intel/cannonlake_rvp: Update board name	Lijian Zhao
2017-10-20	soc/intel/cannonlake: Add platform.asl	Lijian Zhao
2017-10-20	soc/intel/skylake: update GNVS with SGX data	Pratik Prajapati
2017-10-20	soc/intel/apollolake: update GNVS with SGX data	Pratik Prajapati
2017-10-20	intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS	Pratik Prajapati
2017-10-20	soc/intel/skylake: Add GNVS variables and include SGX ASL	Pratik Prajapati
2017-10-20	soc/intel/apollolake: Add GNVS variables and include SGX ASL	Pratik Prajapati
2017-10-20	intel/common/acpi: Add common SGX ASL	Pratik Prajapati
2017-10-20	vendorcode/amd/pi/00670F00: Remove S3 restore functions	Martin Roth
2017-10-20	soc/amd/common: Set AltImageBasePtr to 0	Martin Roth
2017-10-20	Stoney Ridge Platforms: cast AGESA tables to void *	Martin Roth
2017-10-20	Stoney Ridge Platforms: Make AGESA callout tables common	Martin Roth
2017-10-20	mainboard/pcengines/apu2: add apu3 and apu5 variants	Kamil Wcislo
2017-10-19	soc/amd/stoneyridge: Use macros for PCI_DEVFN calls	Chris Ching
2017-10-19	soc/amd/stoneyridge: Replace magic registers	Richard Spiegel
2017-10-19	intel/fsp: Update cannonlake FSP header	Lijian Zhao
2017-10-19	soc/intel/cannonlake: Fix HECI error on reset	Lijian Zhao
2017-10-19	soc/intel/cannonlake: Use EBDA structure to store soc reserve memory size	Subrata Banik
2017-10-19	soc/intel/skylake: Use EBDA structure to store soc reserve memory size	Subrata Banik
2017-10-19	soc/intel/cannonlake: Add IGD Support and pre-OS display code	Abhay Kumar