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2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode). No change of behaviour intended. Refactor FAM10 fidvid . prep_fid_change was already long and it'd get longer with forthcoming patches. We now take apart VSRamp in step b of 2.4.1.7 BKDG to its own function. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27Add 300 MHz and 500 MHz HT frequency limitsXavi Drudis Ferran
Needed to build successfully with Expert mode enabled. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Following patch fills in the callbacks for PCIe x16 resets. This board uses ↵Rudolf Marek
GPM8,GPM9 as reset toggles. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Add support for the ASRock E350M1, an AMD family 14h Fusion board.Scott Duplichan
A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26It adds support for automatic PSS object generation for AMD pre fam Fh CPU. ↵Rudolf Marek
Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons. Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG. Signed-off-by: Rudolf Marek <r.marek@asssembler.cz> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24Add compile-time defaults to some K8 CMOS options in case they're absent in CMOSJosef Kellermann
This affects the CMOS options iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selects. If they're absent in cmos.layout, a Kconfig value is used if it exists, or a hardcoded default otherwise. [Patrick: I changed the ramstage CMOS handling a bit, and dropped the reliance of hw_scrubber on ECC RAM, as it has nothing to do with it - it's the cache that's being scrubbed here.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600Josef Kellermann
coreboot used to set the chipset to IDE mode unconditionally. Now, the user has a couple of ways to choose the configuration: - If a CMOS variable sata_mode exist, it is used to decide if IDE or AHCI is to be used as interface. - If not, a Kconfig option is used. - If unchanged, the Kconfig option is set to IDE. So unless the cmos.layout is extended or Kconfig is modified, this won't change behaviour. [Patrick: Compared to Josef's version, I changed the Kconfig option to be boolean, instead of a magic string. Also, the "IDE" default is handled in Kconfig, instead of an additional line of code.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24Tyan/s2735 doesn't need to define its own hard_reset function anymore.Patrick Georgi
The southbridge already provides hard_reset. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376 ↵Scott Duplichan
2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-21[i945] Add SPD adress mappingSven Schnelle
The current code works only with dual channel if Channel 0 uses SPD address 0x50/0x51, while the second channel has to use 0x52/0x53. For hardware that uses other addresses (like the ThinkPad X60) this means we get only one module running instead of both. This patch adds a second parameter to sdram_initialize, which is an array with 2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single DIMM socket. If NULL is given as the second parameter, the code uses the old addressing scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-19It turns out that the code which enables specific LDN is somewhat buggy.Rudolf Marek
Instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it. I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Fix build errors introduced in r6367Alexandru Gagniuc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Add ACPI code for Lenvo X60Sven Schnelle
It currently supports: - Sleepbutton - AC state - Battery state - Interrupt routing - Display Brightness control - Hotkeys Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Extended K8T890 driver to include the K8T800 and K8M800 northbridgesAlexandru Gagniuc
The K8T800 is almost identical to the K8T800Pro, also added to this patch. The K8T800_OLD is also defined, which is an older version of the K8T800, but which has no driver and early HT code yet. Also extended the K8M890 VGA driver to work for the K8M800 (not tested). According to the datasheet, the K8T890 and K8T800 are similar enough to be able to use the same initialization code. At least for the K8T800, this is sufficient to have a working HT link with the CPU, and to initialise the V-Link to the southbridge. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Lenovo ThinkPad X60: Enable SMI handlerSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15Remove more files and lines mistakenly copied from Roda to X60Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15Remove ACPI mistakenly copied from Roda to ThinkPad X60Peter Stuge
It is incorrect, and will be replaced with proper ACPI for X60. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be ↵Marc Jones
addded by the developer if needed. Fixes abuild issues. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15SERIAL_POST was renamed to CONSOLE_POST a while agoStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Lenovo ThinkPad X60 / X60s SupportSven Schnelle
Adds support for Lenovo X60 series ThinkPads. So far, only X60s (Model 1703) has been tested. It's a basic patch without SMI and ACPI, as this makes it easier to review. SMI and ACPI patches will follow. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Errata #169 works on HT, not MCJosef Kellermann
Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Removed LPC DMA Deadlock workaround...Josef Kellermann
Setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in amdk8/coherent.c Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Fix Typo. (and why is that file, and some of its siblings per-board?)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.Frank Vibrans
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14This code provides support for the superio chip on the AMD Inagua platform ↵Frank Vibrans
(not commercially available). It is independent of the AMD>code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.Frank Vibrans
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Marc Jones <marcj303@gmail.com git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 This code provides support for the superio chip on the IBASE Technology ↵Frank Vibrans
DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14This code fixes a number of build issues related to the AMD Agesa code. The ↵Frank Vibrans
particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Add AMD cpu wrapper code. Patch 4 of 8.Frank Vibrans
This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 This code provides southbridge initialization for SB800 south bridges. It ↵Frank Vibrans
is dependent on the AMD CIMx/SB800 code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14This code provides cpu northbridge initialization for Family 14h cpus. It is ↵Frank Vibrans
dependent on the AMD Agesa code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.Frank Vibrans
This code currently generates many warnings that are functionally benign. These are being addressed, but the wheels of bureaucracy turn slowly. This drop supports AMD cpu families 10h and 14h. Only Family 14h is used as an example in this set of patches. Other cpu families are supported by the infrastructure, but their specific support is not included herein. This patch is functionally independent of the other patches in this set. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-12Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early ↵Rudolf Marek
only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only... Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc... Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad. Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded. While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10According to AMD documentation, cache type WP should be used forScott Duplichan
execution from flash memory. Coreboot uses WB. While there is no noticeable performance difference between the two settings, use of WB can cause a problem for a jtag debugger. The attached patch changes AMD cache as ram setting for flash execution from WB to WP. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10RS690: Provide support for MMCONF.Josef Kellermannseppk
If enabled, set up 0xe0000000..0xf0000000 as MMCONF area. Must still be configured in per-board ACPI for the OS to pick it up, so it's disabled by default. Signed-off-by: Josef Kellermann<seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10Implemented workaround for erratum 169, obsoleting erratum 131.Alexandru Gagniuc
Workaround for 131 removed. Changed workaround for erratum 110 to only include pre-revision-F processors. For details, check AMD publications: #25759 (Errata for Fam F pre-revision F processors) #33610 (Errata for Fam F revision F and later processor) Based on work and previous patches by: Rudolf Marek <r.marek@assembler.cz> Josef Kellermann <seppk@arcor.de> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10Fix a potential system hang by handling AMD Model F Erratum 89Josef Kellermann
a bit later. Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-08Place the W83627EHG MIDI base address mask in the correct position.Alexandru Gagniuc
Corrects "index 98 has no mask" error at runtime. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Jonathan Kollasch <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-07Reliably build arbitrary Kconfig-based revisions of SeaBIOSPeter Stuge
Reliability is accomplished by checking out the desired SeaBIOS commitish into a branch named 'coreboot' in the local SeaBIOS git repository. Using a branch allows TAG-$(CONFIG_SEABIOS_..) to refer to any commitish in the SeaBIOS git repo, not just branches and tags. Configuration is done with make defconfig followed by enabling and disabling of the relevant coreboot-specific SeaBIOS options by appending to .config using echo. This works, because later entries in .config will overwrite earlier ones. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-05Actually add PC87382 into Kconfig, missing from r6332Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-05Add PC87392 supportSven Schnelle
This adds support for the NSC PC87392 Super I/O. It is used in Lenovo Docking Stations as Super I/O chip. v2 because of: - skip some empty files - missing newlines in Kconfig and Makefile.inc - add the Kconfig option in sorted order Thanks to idwer on irc for pointing that out. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-05Add PC87382 supportSven Schnelle
This patch adds support for NSC PC87382 Super I/O. It is used in many Lenovo Notebooks as Docking LPC Switch. v2 because of: - Skip some empty files - Fix newlines in Kconfig and Makefile.inc - chip.h missed uart8250.h include - add the Kconfig option in sorted order Thanks to idwer on irc for pointing that out. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03Fix subvendor/subdevice programming on RS690Josef Kellermann
Some RS690 devices require subvendor/subdevice IDs to be programmed at locations other than default 0x2c. Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-03Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functionsPatrick Georgi
This is so that boards can determine them on runtime based on hardware properties, if so desired. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-02pmh7.[ch]: Add missing license headers.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01Properly add Lenovo EC to buildSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01Add support for the Lenovo PMH7 embedded controllerSven Schnelle
Lenovo PMH7 (Power Management Hardware Hub) is found in most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-31Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot ifStefan Reinauer
a rare condition arises. Based on findings by Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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