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2019-01-23mb/google/octopus: Override emmc DLL values for MeepKane Chen
New emmc DLL values for Meep. BUG=b:122308271 TEST=Boot to OS on 13 Meep system Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/31021 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Add BMC KCS to ACPITimothy Pearson
The BMC KCS interface must be advertised to the host OS in order for automatic load of the ipmi module to work. Expose the KCS interface via ACPI. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19822 Reviewed-by: Piotr Kubaj <pkubaj@anongoth.pl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/asus/kgpe-d16: Enable IPMI KCS accessTimothy Pearson
The on-board BMC contains a hardware KCS interface. Allow access to it over LPC. Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac6 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/c/19821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"Daniel Kurtz
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b. Reason for revert: It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config, not its SCI configuration. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Boot grunt, does not go to recovery screen Change-Id: I500934f3e03e66c97873accd4a979a23d4509675 Reviewed-on: https://review.coreboot.org/c/30997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-22AGESA/binaryPI: Add NULL pointers checkKyösti Mälkki
Fix regression after commits 4ad7f5b AGESA: Use pcidev_on_root() 33ff44c binaryPI: Use pcidev_on_root() Previously used call dev_find_slot() returned pointers to PCI device nodes that were actually not present in the hardware at all. Register reads would come back with invalid (0xff) values and writes would be ignored. After change to pcidev_on_root(), attempting to do register operations with non-present PCI hardware immediately halts with error get_pbus: dev is NULL! Change-Id: I785350c171a642207c5fab884a953d45a3bfe592 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-22cpu/intel/model_206ax: Use parallel MP initArthur Heymans
This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR'sArthur Heymans
Intel pineview has the same alternative SMRR MSR and IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for that before enabling this feature. This also exposes a function to fetch whether alternative SMRR MSR's ought to be used. Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30868 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22mb/google/hatch: Remove MAINBOARD_USES_IFD_EC_REGION selectionSubrata Banik
hatch shouldn't make use of internal ec.bin through IFD tool. Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-21Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios"Raul Rangel
This reverts commit b82afce18aff24b6e5e3b73a67a6533cc4865a26. Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit. e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch. We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs. Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-21lib/boot_device: Add API for write protect a regionRizwan Qureshi
Add API that should be implemented by the boot media drivers for write-protecting a subregion. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/28724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-21drivers/spi: Add controller protection typeRizwan Qureshi
Some SPI controllers support both READ and WRITE protection add a variable to the protect API for the callers to specify the kind of protection they want (Read/Write/Both). Also, update the callers and protect API implementation. BUG=None BRANCH=None TEST=test that the mrc cache is protected as expected on soraka. Also tried if the read protection is applied correctly. Change-Id: I093884c4768b08a378f21242ac82e430ac013d15 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/30559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-20mb/google/octopus/variants: Disable xHCI compliance mode for FleexAmanda Huang
Some usb devices exhibits signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:120009029 TEST=Verified usb operation successfully. Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-20mb/google/octopus/variants/meep: Disable xHCI compliance modeWisley Chen
Some usb devices exhibit signal loss which causes xHCI entering compliance mode. The resolution is to disable xHCI compliance mode. BUG=b:122671995 TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link control" register and usb operation successfully. Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/30948 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-20src/soc/intel/braswell: Use DEVICE_NOOPElyes HAOUAS
Use already defined DEVICE_NOOP instead. Change-Id: Ie6182f273cba3073c84a502c34a002dee6122c2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29857 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLEVanessa Eusebio
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18mb/google/sarien/variants: Add Thermal Sensors informationSumeet Pawnikar
Add available thermal sensors information for CPU throttling action. BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-18drivers/spi/winbond.c: Add the rest of >=1MB Winbond W25 chipsMike Banon
Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I4d15d5acf0e2044e5128ce809c282fbcb35f24f0 Reviewed-on: https://review.coreboot.org/c/30746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-18mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet specDtrain Hsu
After adjustment on Sarien EVT TouchScreen: 380.7 KHz TouchPad: 379.3 KHz H1: 392.2 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Reviewed-on: https://review.coreboot.org/c/30949 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17mb/lenovo/x220: Add x1 as a variantBill XIE
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstageArthur Heymans
With the i82801gx code automatically disabling devices ethernet NICs attached to the southbridge PCIe ports can now be disabled during the ramstage. Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30245 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17sb/intel/i82801gx: Implement PCIe coalescingArthur Heymans
The implementation is a simplified version of the haswell/broadwell code. This also adds a chip option to enable coalescing from the devicetree. Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-17vendorcode/{amd,cavium,intel}: Remove trailing whitespacePeter Lemenkov
find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \; Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30959 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17superio/nsc: fix IO masksFelix Held
The IO mask shouldn't contain zeros inside the block of ones. Change-Id: Icfebbf1d1d88ceef58800339bf899931fdc61ab7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/30954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-17soc/intel/cannonlake: drop extra newlinePatrick Georgi
Change-Id: I614ea7f0f74326e306649779266001cf25ce5e07 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-01-17cpu/intel/car: Remove unneeded white spaceElyes HAOUAS
Change-Id: Ib711560838ee0b5cd317ec573e97c4004751d3ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30952 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17console/init: Print log level in coreboot bannerPaul Menzel
Sometimes, it’s not clear, what log level is configured (in Kconfig and CMOS), so print the log level in the banner. coreboot-4.9-354-gff6e99cebe Tue Jan 15 15:23:20 UTC 2019 bootblock starting (log level: 7)... Change-Id: I82c87ae90cd53fd47458fc6df3ef2c7f238f0f3d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/30935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17tss/tcg-2.0: remove unnecessary break from marshaling codeJoel Kitching
BUG=None TEST=None Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/29652 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17lib/libgcc.c: Fix shift warningsPaul Menzel
``` if (!(a & (0xffff << 16))) { ^~ src/lib/libgcc.c:40:18: error: result of '255 << 24' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] if (!(a & (0xff << 24))) { ^~ src/lib/libgcc.c:45:17: error: result of '15 << 28' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] if (!(a & (0xf << 28))) { ^~ ``` Change-Id: I7bdd75c20a76b303743d7e7e0d3a6503760284fd Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/23361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-17mb/google/hatch: Configure miscellaneous featuresRonak Kanabar
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set speed_shift_enable = 1 To Enable Speed Shift Technology support Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/30774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-17soc/intel/cannonlake: Change in SaGv optionsRonak Kanabar
CNL,WHL and CFL all are not using midfixed option in SaGv so keeping it for CNL only and removing it for others. Change-Id: I754515c2f8e249479c603872c61ac9a006e962ff Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/30917 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17soc/intel/icelake: Fix AG3E programming in PMCLijian Zhao
According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped register but not pci configuration spaces, hence change the programming method in icelake pmc driver. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7 Reviewed-on: https://review.coreboot.org/c/30947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-17src/mainboard/google/sarien: query recovery mode from Cr50Keith Short
On the Sarien/Arcada platforms, the EC is not trusted to provide the state of the ESC+REFRESH+PWR recovery combination. On these platforms the Cr50 latches the state of REFRESH+PWR for use as the recovery mode key combination. BUG=b:122715254 BRANCH=none TEST=Verify recovery mode screen shown after pressing REFRESH+PWR Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/30937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17src/security/tpm: query recovery mode from Cr50Keith Short
On the Sarien/Arcada platforms, the EC is not trusted to provide the state of the ESC+REFRESH+PWR recovery combination. On these platforms the Cr50 latches the state of REFRESH+PWR for use as the recovery mode key combination. BUG=b:122715254 BRANCH=none TEST=Verify recovery mode screen shown after pressing REFRESH+PWR Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ie3ce519956f916023c8c52f1d11fa93331f52f3c Reviewed-on: https://review.coreboot.org/c/30929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-17soc/intel/fsp_broadwell_de: Enable FIT supportPatrick Rudolph
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Tested on wedge100s. Microcode is placed in FIT. Change-Id: Ie0003f597aa5f272847b4f8895a1e3571caa3464 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30956 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17soc/intel/fsp_broadwell_de: Fix TSEG size computationPatrick Rudolph
The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on comparison. The result is that the limit is effectively FFFFFh. Add one MiB to the register value to make TSEG 8MiB instead of 7MiB. Fixes a crash related to SMRR not matching the TSEG region. Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-17hatch: Add sbmios_mainboard_sku functionShelley Chen
BUG=b:122578255 BRANCH=None TEST=mosys platform id/name/family Change-Id: I6288ea1a4e9f692b6e04440e61f59ea53f01ebec Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17hatch: disable sw syncShelley Chen
Disabling software sync since EC patches haven't landed yet. BUG=b:120914069 BRANCH=None TEST=build bios image and make sure gbb flag 0x200 is set Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17riscv: create Kconfig architecture features for new partsRonald G. Minnich
RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/30348 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mb/google/sarien/variants/sarien: Set up tcc offset for sarienJohn Su
Change tcc offset from 15 to 3 for sarien. BUG=b:122636962 TEST=Match the result from TAT UI Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30808 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16soc/intel/cannonlake: Fix afterg3 programmingLijian Zhao
According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC memory mapped register but not pci config spaces. Change the programming to affect that difference. BUG=b:122425492 TEST=Change System Power State after failure to "s5 off", and boot up onto sarien platform, check the register with iotools mmio_read32 0xfe001020 and bit 0 is set. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e Reviewed-on: https://review.coreboot.org/c/30945 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mainboard/google/kahlee: Also configure GPIO_9 in RAM stageDaniel Kurtz
The general rule is to configure GPIOs used by coreboot in bootblock (using the reset table), and GPIOs used by OS in RAM stage. However, GPIO_9 will be used as both, and we need to reconfigure it to properly set up debounce, however, it is no longer possible to change bootblock, so we also configure it in RAM stage to make the new debounce configuration take affect. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03 Reviewed-on: https://review.coreboot.org/c/30922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-16soc/amd/stoneyridge/gpio: Configure debounce for irq gpiosDaniel Kurtz
FT4 has a strange property where whenever the debounce registers for any one gpio are changed, the FT4 disables interrupt propagation for ALL gpio irqs for ~4ms. In other words, if an edge interrupt of one gpio happens exactly during this debounce-irq-off window immediately following the configuration of another gpio, the interrupt will be lost. It is quite difficult to deal with this in the kernel, since during kernel boot time, drivers & devices are probed asynchronously, meaning it may happen that an already loaded driver may miss an interrupt when some later driver is being probed and configuring its gpio interrupt. To eliminate this possibility, we pre-configure the debounce registers in ram stage for all gpios that will be used as irqs later by the kernel using the same configuration as used by the kernel, as per this table: IRQ Debounce Edge Remove Glitch Level High Preserve Low Glitch Level Low Preserve High Glitch Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I94c7ecfb14e5bb209b3598e10287c80eb19da25b Reviewed-on: https://review.coreboot.org/c/30921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-16soc/amd/stoneyridge/gpio: Remove redundant definitionsDaniel Kurtz
Thes are already defined identically ~20 lines above. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=none BRANCH=none TEST=compile Change-Id: Ic3faeb97788b2b524345cdbfb368e98d43bac075 Reviewed-on: https://review.coreboot.org/c/30920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-16mb/google/kahlee/careena: Add 20ms delay to captureAkshu Agrawal
define wakeup-delay-ms to 20ms. This avoids the pop noise heard at the start of capture. BUG=b:119926436 TEST=with kernel patch https://lore.kernel.org/patchwork/patch/1029806/ no pop sound heard at start of capture Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/c/30726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mb/google/kahlee/liara: Add 20ms delay to captureAkshu Agrawal
define wakeup-delay-ms to 20ms. This avoids the pop noise heard at the start of capture. BUG=b:119926436 TEST=with kernel patch https://lore.kernel.org/patchwork/patch/1029806/ no pop sound heard at start of capture Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/c/30725 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16drivers/generic/adau7002: Add wakeup-delay-ms propertyAkshu Agrawal
Passes out wakeup-delay to driver. This delay is applied at the start of capture to make sure dmics are ready before we start recording. This avoids pop noise at begining of capture. BUG=b:119926436 TEST= With kernel patch https://lore.kernel.org/patchwork/patch/1029806/ No pop sound heard at start of capture Change-Id: I32b18bf80fad5899ab4093a127dfd52d589bc365 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/c/30724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-16string.h: Add isprint()Nico Huber
Change-Id: If179687f0a15cf5b16723ad18d8eb86a2d5fa48d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/29479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16mb/purism: Select NO_POST instead of overriding its dependenciesNico Huber
Declaring a Kconfig symbol ahead to override its default also always sets implicit dependencies. If the original symbol doesn't have any, Kconfig gets confused. Change-Id: Ie6d9ca96e4b6037eefd432dd386cb5e540deb0ed Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16nb/intel/sandybridge: Remove the C native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16mainboard/intel: Update mainboard UART KconfigSubrata Banik
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged, all mainboard using intel cannonlake,coffeelake, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. TEST=Intel client and IoT team has verified that LPSS uart is working fine on CNL, WHL and ICL RVPs. Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30913 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 20:17:19 +0000