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AgeCommit message (Expand)Author
2013-12-30AMD K8 (rev F): Move rev F0/F1 workaround to headerKyösti Mälkki
2013-12-30AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridgeKyösti Mälkki
2013-12-30AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORTKyösti Mälkki
2013-12-30AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORTKyösti Mälkki
2013-12-29AMD K8 (rev-F): Always have RAMINIT_SYSINFOKyösti Mälkki
2013-12-29AMD fam10: Drop RAMINIT_SYSINFOKyösti Mälkki
2013-12-29via/epia-m700: Drop RAMINIT_SYSINFOKyösti Mälkki
2013-12-29AMD K8: Socket implies K8_REV_F_SUPPORTKyösti Mälkki
2013-12-27via: Write »access« without »m« at endPaul Menzel
2013-12-26AMD AGESA: Drop MEM_TRAIN_SEQKyösti Mälkki
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
2013-12-26vortex86ex: Cleanup earlymtrr.c includeKyösti Mälkki
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
2013-12-23usbdebug: Add option to disable console for romstageKyösti Mälkki
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
2013-12-22Fix linking microcode with more than one microcode fileAlexandru Gagniuc
2013-12-22vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.Andrew Wu
2013-12-21lynxpoint: XHCI: Don't put device in D3 in _PS0 MethodDuncan Laurie
2013-12-21lynxpoint: Fix an issue clearing port change status bitsDuncan Laurie
2013-12-21lynxpoint: XHCI: Advertise D3 as lowest wake stateDuncan Laurie
2013-12-21lynxpoint: Fix issues with XHCI initDuncan Laurie
2013-12-21lynxpoint: Route all USB ports to XHCI in finalize stepDuncan Laurie
2013-12-21lynxpoint: Move USB SMI sleep code to separate USB filesDuncan Laurie
2013-12-21pit: disable LCD FETs before doing any graphics initDavid Hendricks
2013-12-21exynos5420: Assign corect parent PLLsDavid Hendricks
2013-12-21exynos5420: don't assume MPLL for i2c parent clockDavid Hendricks
2013-12-21exynos5420: Set SPLL to 400MHzDavid Hendricks
2013-12-21exynos5420: re-factor clock_get_periph_rate()David Hendricks
2013-12-21exynos5420: add a peripheral clock select --> PLL decoderDavid Hendricks
2013-12-21exynos5420: add CPLL and DPLL to the known list of PLLsDavid Hendricks
2013-12-21exynos5420: correct the PMS value for CPLLDavid Hendricks
2013-12-21exynos5420: Configure the UART pins unconditionallyGabe Black
2013-12-21exynos5250: Implement support to boot with USB A-A firmware uploadJulius Werner
2013-12-21armv7: Allow accessing ACTLR (Auxiliary Control Register)Hung-Te Lin
2013-12-21exynos5420: re-factor the SDMMC GPIO config routinesDavid Hendricks
2013-12-21exynos5420: configure SD_0_CDn as VDDEN for eMMCDavid Hendricks
2013-12-21armv7: Add CPU & MP primitive instructionsHung-Te Lin
2013-12-21exynos5420: init APLL at 1800MHzDavid Hendricks
2013-12-21exynos5xxx: use oscillator clock when changing ARM frequencyDavid Hendricks
2013-12-21exynos5420: set L2ACTLR parameters for A15 coresDavid Hendricks
2013-12-21snow: Set up the i2s0 pins during bootGabe Black
2013-12-21exynos5250: Add a pinmux function to set up i2s bus 0Gabe Black
2013-12-21armv7: add wrappers to read/write L2ACTLRDavid Hendricks
2013-12-21ARM: Don't inject nobits since we actually want to load these bitsGabe Black
2013-12-21ARM: Remove (NOLOAD) from the .car sectionGabe Black
2013-12-21exynos5420: minor correction to CPU frequency printDavid Hendricks
2013-12-21armv7/exynos: Fix and remove memory reset workaroundsHung-Te Lin
2013-12-21Pit: graphicsRonald G. Minnich
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