coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS
2020-07-26	mb/emulation/qemu-aarch64: Fix up license header	Angel Pons
2020-07-26	/mb/google/volteer/*/gpio.h: Fix up license header	Angel Pons
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-07-26	mb/intel/saddlebrook/devicetree.cb: Use PCH_IRQ* macros	Angel Pons
2020-07-26	device/device.h: Add `is_dev_enabled` function	Angel Pons
2020-07-26	cpu/intel/model_206ax: Clean up includes	Elyes HAOUAS
2020-07-26	src: Remove unused include <cpu/x86/smm.h>	Elyes HAOUAS
2020-07-26	src: Remove unused 'include <cpu/intel/common/common.h>	Elyes HAOUAS
2020-07-26	mb/google/zork: remove ACPI_FADT_RESET_REGISTER from fadt_flags	Felix Held
2020-07-26	mb/amd/mandolin: add default USB2 PHY tune parameters to devicetree	Felix Held
2020-07-26	amd/picasso: rework USB2 PHY tune parameter handling	Felix Held
2020-07-26	soc/skylake: Configure SATA options only if SATA is enabled	Felix Singer
2020-07-25	soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters	Felix Held
2020-07-25	soc/intel/baytrail/southcluster.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/include/soc/irq.h: Add braces	Angel Pons
2020-07-25	soc/intel/baytrail: Simplify pattrs definitions	Angel Pons
2020-07-25	soc/intel/baytrail/smm.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/smihandler.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/cpu.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/sd.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/lpss.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/lpe.c: Align with Braswell	Angel Pons
2020-07-25	mb/intel/cedarisland: undo set trig and bufdis for NF pads	Maxim Polyakov
2020-07-25	soc/intel/{baytrail,braswell}: Drop unneeded `return`	Angel Pons
2020-07-25	soc/intel/baytrail/iosf.c: Add missing braces	Angel Pons
2020-07-25	soc/intel/baytrail/elog.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/cpu.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/acpi.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/bootblock/bootblock.c: Move functions	Angel Pons
2020-07-25	soc/intel/baytrail: Retype some pointers	Angel Pons
2020-07-25	soc/intel/tigerlake: Update Pkg C-State latencies	Ravi Sarawadi
2020-07-25	src/include/ramdetect.h: Add missing includes	Elyes HAOUAS
2020-07-25	nb/intel/ironlake/raminit.c: initialize 'reply.command'	Elyes HAOUAS
2020-07-25	nb/intel/haswell/hostbridge_regs.h: Clean up registers	Angel Pons
2020-07-25	mb/getac/p470/acpi_tables.c: Remove wrong comment	Elyes HAOUAS
2020-07-25	sb/intel/bd82x6x: Use common irqlinks.asl	Angel Pons
2020-07-25	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	Sumeet R Pawnikar
2020-07-25	soc/intel/tigerlake: Update Tiger Lake SA IDs	Derek Huang
2020-07-24	soc/amd/picasso: mark usb2_phy_tune struct as packed	Felix Held
2020-07-24	mb/supermicro/x11-lga1151: Clean up gpio.h	Maxim Polyakov
2020-07-24	supermicro/x11-lga1151/gpio: 4/4 Convert field macros to PAD_CFG	Maxim Polyakov
2020-07-24	supermicro/x11-lga1151/gpio: 3/4 Fixes some field macro	Maxim Polyakov
2020-07-24	supermicro/x11-lga1151/gpio: 2/4 Exclude fields for PAD_CFG	Maxim Polyakov
2020-07-24	mb/google/volteer: Remove unused dptf.asl files	Tim Wawrzynczak
2020-07-24	assert.h: Do not use __FILE__ nor __LINE__ on timeless builds	Angel Pons
2020-07-24	nb/intel/sandybridge: Put host bridge registers into its own file	Angel Pons
2020-07-24	nb/intel/haswell: Put host bridge registers into its own file	Angel Pons
2020-07-24	device/pci_device.c: Do not complain about disabled devices	Angel Pons
2020-07-24	supermicro/x11-lga1151/gpio: 1/4 Decode raw register values	Maxim Polyakov