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2020-03-06soc/mediatek/mt8183: Do TX tracking for DRAM DVFS featureHuayang Duan
The TX window will offset to edge during DVFS switch, which may cause TX data transmission error and random kernel crash. Therefore, use the standard dqsosc (DQS Oscillator) for TX window tracking. BUG=b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-03-06soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switchHuayang Duan
Because eMCP and discrete DDR devices have different DVFS tables, their EMI bandwidth thresholds should also be different. When the EMI total bandwidth reaches the threshold, the system will notify DVFS module to perform DVFS switch for system performance in low power states. This patch increases the threshold from 0xa to 0xd for eMCP DDR devices so that DVFS switch will be less likely to happen. The register table of EMI_BWCT0 is incorrect in the datasheet. According to the hardware design, BW_2ND_INT_BW_THR should be in bits [30:24] instead of [22:16]. However, the logic in DRAM driver is correct, aligned with the hardware design, so we don't need to correct it. BRANCH=kukui BUG=b:142358843 TEST=bootup pass Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39034 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/up/squared: move USB config to device treeMaxim Polyakov
Change-Id: Ic4db37112e7b2329f9e4885139deca12557ffe3a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39134 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/up/squared: remove NpkEn option from romstageMaxim Polyakov
There is no need to set the NpkEn option to disable the NPK device, since it has already been done in the devicetree. Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06soc/apl: add options to override USB port configMaxim Polyakov
Allows to override the PortUsb20Enable and PortUsb30Enable FSP options (which are set to 1 by default) to enable/disable USB ports if the usb_config_override flag is set to "1". Therefore, these changes will not affect other boards with an Apollo Lake processor. Change-Id: Ia94a2be1647f7743ef0c918ae3b34437a179261c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06mb/google/volteer: add new ripto variantNick Vaccaro
Add a new ripto variant based off of the volteer baseboard design. BUG=b:148385924, b:150810535 TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image and verify ripto boots to the kernel. Change-Id: If7606588147500a465f16c7846e2c8429ece93ec Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-03-06mb/google/volteer: make variant_early_gpio_table weakNick Vaccaro
Declare variant_early_gpio_table() weak to allow override by variants. BUG=b:148385924, b:150810535 TEST=none Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39300 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06mb/lenovo/*: Add support for VBOOT on 12MiB devicesJonas Moehle
Enable VBOOT support on all devices that have a 12 MiB flash, using RW_MAIN_A + RW_MAIN_B partition, allowing the use of tianocore payload in both RW_MAIN_A, RW_MAIN_B and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_AB by default The VBNV is intentionally not covered by the CMOS checksum. Tested on x230 and T440p. Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Jonas Moehle <ad-min@mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-03-06nb/intel/haswell/peg: Add PEG driver stubChris Morgan
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the Haswell northbridge. This code is necessary to support the dGPU of the t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated to the correct Haswell values. Tested on t440p with dGPU on Ubuntu 18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is unable to read the VBIOS of the dGPU as it has an invalid checksum (I checked that the ROM in CBFS is correct). With this patch DRM works correctly with both the Nouveau driver and the Nvidia proprietary driver. Windows 10 1909 also tested but generates bluescreen once GPU driver is loaded. Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-06sb/intel/common/firmware/Makefile.inc: use ifdtool --output flagMarcello Sylvester Bauer
Use the ifdtool --output flag to modify coreboot.pre inplace, instead of using the `mv` command to get the same result. In this way the stdout will make more sense in the build context. Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-06soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference. BUG=CID 1353148 TEST=Built and boot up to kernel. Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06Revert "i82371eb: Drop support for older PIIX chips"Patrick Georgi
This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4. Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore. Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Keith Hui <buurin@gmail.com>
2020-03-06src/arch/x86: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: Ib5a92bb46ff2b9d2928aae3763daec71747044c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-06src/arch/riscv: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are listed in AUTHORS. Change-Id: I770c1afd9b68a40ec0e69818f24b5ef3ad4f1d35 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-06src/arch/ppc64: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: I19b1c379b474dd011e2d0f8c8202ff1351c9290d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06src/arch/arm64: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: Ic5eddc961d015328e5a90994b7963e7af83cddd3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06src/arch/arm: Convert to SPDX license headerPatrick Georgi
This also drops individual copyright notices, all mentioned authors in that part of the tree are already listed in AUTHORS. Change-Id: Ic2bab77edaf7ad97b7f3278cb108226a18cf3791 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-06mb/google/hatch/puff: Enable VBOOT_EC_EFSSam McNally
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP vboot build. BUG=b:150742950 TEST=Puff can boot with EC EFS with hardware write protect enabled BRANCH=none Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I0877000b7d277106436831f2d69775c25299da9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-06security/vboot: Support enabling EC EFS with EC software syncSam McNally
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot build must also enable EC EFS. Add an option to control this, passing it through to vboot. BUG=b:150742950 TEST=none BRANCH=none Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I697e90748e19d15af154011413b30c0f2a0bf52e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-05Revert "acpi: Bump FADT to revision 6"Matt DeVillier
This reverts commit c8b0f31ca1b6cae993736d47d919080b6c186c6f. Bumping the FADT table version from 3 to 6 causes Windows 10 to BSOD with an ACPI BIOS error or simply fail to boot on multiple platforms (Haswell, Broadwell, Braswell, Skylake). Revert until the issue can be properly identified and corrected. Change-Id: I261d953321df2616a3f1c3460a535b57a8848315 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-04soc/intel/denverton_ns: Allow including microcodeFelix Singer
Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Iaa295c74e9c470d5830e22d0b0c73013c7333293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39266 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans
The cache as ram code will use one form of a non-eviction mode. Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04vc/amd/agesa/[...]/Config: Avoid out-of-bounds warningsJoe Moore
The memNTrainFlowControl array is generating Coverity warnings in multiple places in code where it attempts to write to index 1. The array is defined as either 2 elements or 1 of NULL depending on #if (AGESA_ENTRY_INIT_POST == TRUE). This is likely a false alarm from Coverity (memory should not be training outside of a POST), but adding a second NULL element for the AGESA_ENTRY_INIT_POST == FALSE case. Tested on Lenovo G505s. Change-Id: Iaebe0830471e1854d6191c69cdaa552f900ba7a6 Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1357451, 1357452, 1357453 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38176 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04vc/amd/agesa: Delete mfParallelTraining.cJoe Moore
Potential for out-of-bounds read. However, this code is not used on F14, F15tn, or F16kb platforms. As can be seen in vc/amd/agesa/f15tn/Config/PlatformInstall.h only multiple socket F10 is supported. Tested on Lenovo G505s. Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04vc/amd/agesa: Fix uninitialized scalar variableJoe Moore
AllocParams.Persist is used uninitialized when calling HeapAllocateBuffer. This could lead to unpredictable or unintended results. The f15tn and f16 versions of AmdS3Save.c have already addressed this by initializing AllocParams.Persist=0 in the same location in the code, so adding to f14 only. Change-Id: I2cbfbc4ad14a861e0cd92f130209b3b0f5b76a17 Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-04vc/amd/agesa/f14/Proc/Mem: Fix uninitialized variableJoe Moore
Uninitialized variable will contain an arbitrary value left from earlier computations. This issue has already been addressed in the f15tn and f16kb versions of this same file, so am backporting the fix. Change-Id: Id876107265689e08ad6760e514a4911f32b53da7 Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38048 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04vc/amd/agesa/[...]/Proc/Mem: Delete unused functionJoe Moore
The generic MemNProgramNbPstateDependentRegistersUnb function is unused, and generates a Coverity warning of an unused switch case. Only family specific versions of this function are called elsewhere. Delete unused function. Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94 Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241810 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38493 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04src/mainboard/lenovo/t530/Kconfig: Fix PCI device id for the iGPUPrasun Gera
Both T530 and W530 share the same PCI device id of 0166 for the iGPU. Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a Signed-off-by: Prasun Gera <prasun.gera@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04mb/lenovo/t530/devicetree: Select docking_supportedPeter Lemenkov
Looks like it should select it like any other Lenovo xx20/xx30 boards around. UNTESTED. Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04mb/lenovo/t530/devicetree: Drop unnecessary initializationPeter Lemenkov
These two variables are initialized to zero by default. Change-Id: I590f601b5297a9bfa93607442d7e0b8d79f1ab51 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04mb/lenovo/[tw]530/devicetree: Fix comment about chip codenamePeter Lemenkov
Change-Id: I3323e713970041b0665ca17bbcad985cba600687 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04mb/lenovo/t530/*/*/devicetree: Align whitespace and comments across the boardsPeter Lemenkov
Only whitespace changes, minor comments. This helps making diff between devicetrees shorter. Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04nb/intel/nehalem: Use cache.h functionsArthur Heymans
Some local functions need renaming to avoid name collision. Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37195 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04nb/amd/agesa/family14/acpi: Fix commentElyes HAOUAS
"amdfam10" is no more. Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38054 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04include/cpu/amd: Drop unused filesElyes HAOUAS
Change-Id: Iff14250e52854d598967cfd3cbc98061be06e581 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38055 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04soc/intel/skylake/elog: fix BUG: pch_log_rp_wake_source requests hiddenMichael Niewöhner
The current elog implemetation searches for an active PME status bit by iterating the PCI devices. On disabled or hidden devices a BUG gets triggered: BUG: pch_log_rp_wake_source requests hidden ... This is caused by the use of the PCH_DEV_* macros which resolve to _PCH_DEV and finally call pcidev_path_on_root_debug. Disabled devices are skipped already so we can safely use the DEVFNs instead, circumventing the BUG. Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-03-04cpu/intel/model_206ax: Lock MSR on all coresPatrick Rudolph
Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one handling APM_CNT_FINALIZE. Tested on HP Z220: FWTS no longer reports this as an issue. Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-04cpu/microcode: Fix config CPU_MICROCODE_CBFS_EXTERNAL_BINSNico Huber
Make the variable override for CPU_MICROCODE_CBFS_EXTERNAL_BINS local to the target. Otherwise, `cpu_microcode_bin +=` lines that are evaluated after `src/cpu/Makefile.inc` still append to it. Change-Id: If81f307afc325ff3c1e987e9483ed5e45fdc403e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-04soc/intel/tigerlake: Update SerialIoUart settings for Tiger LakeSrinidhi N Kaushik
update SerialIoUartAutoFlow settings for Tiger Lake platform. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04soc/intel/denverton_ns: Allow using FSP repoFelix Singer
This commit is adding a dependency check for the FSP_USE_REPO config option which so far was not able to deal with Denverton systems. Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-03-04src/ec,mainboard: Move weak smbios_system_sku() override inwardsEdward O'Callaghan
Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c implementation and simply wrap a call to: google_chromeec_smbios_system_sku(). BUG=b:150735116 BRANCH=none TEST=none Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04mainboard/google/dedede: Migrate onto SKU ID/fw_config helpersEdward O'Callaghan
Leverage the common sku id space helper encoders. dedede uses the non-legacy SKU ID space. squash in, mainboard/google/dedede: Migrate onto get fw_config helper BUG=b:149348474 BRANCH=none TEST=only tested on hatch Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-04mainboard/google/octopus: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders and set the sku id max to 0xff for legacy to ensure we behave the same. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-03sb/lynxpoint: hook up smmstoreMatt DeVillier
Adapted from implementation in sb/intel/common. Test: build/boot variants of google/{beltino,slippy} with Tianocore and SMMSTORE enabled Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03mb/asrock/h110m: Explain why some SATA ports are emptyMaxim Polyakov
Change-Id: Ib0a24fab22ee082367b82b3e8ee7383f1f02a4ad Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03soc/intel/apl: disable NPK device in devicetree.cbMaxim Polyakov
Allows to enable/disable NPK device from the device tree: device pci 00.2 off end # NPK Tested on Kontron come-mal10. Change-Id: I910245d4ff35a6a0a9059fb6911d4426cdb999b6 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38814 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03soc/intel/gpio_defs: add a new macro for pad configMaxim Polyakov
Adds PAD_CFG_NF_BUF_IOSSTATE_IOSTERM macro to configure native function, iosstate, iosterm and disable input/output buffer. This is used in the pad configurations for the Kontron COMe-mAL10 module board [1]. [1] https://review.coreboot.org/c/coreboot/+/39133 Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger LakeSrinidhi N Kaushik
Update FSPM header to add Vtd related Upds for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-03mb/google/drallion: Enable cbfs SAR valueEric Lai
Enable read SAR value from cbfs. BUG=b:150347463 TEST=NA Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-09 01:29:32 +0000