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2015-04-02vpd: retrieve mac addresses and pass them to bootloaderVadim Bendebury
Chrome OS devices firmware usually includes an area called VPD (Vital Product Data). VPD is a blob of a certain structure, in particular containing freely defined variable size fields. A field is a tuple of the field name and field contents. MAC addresses of the interfaces are stored in VPD as well. Field names are in the form of 'ethernet_macN', where N is the zero based interface number. This patch retrieves the MAC address(es) from the VPD and populates them in the coreboot table so that they become available to the bootloader. BUG=chrome-os-partner:32152, chromium:417117 TEST=with this and other patches in place the storm device tree shows up with MAC addresses properly initialized. Change-Id: I955207b3a644cde100cc4b48e51a2ab9a3cb1ba0 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 1972b9e97b57cc8503c5e4dc496706970ed2ffbe Original-Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219443 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Samus: Synchronization with FRC to enable PCIe Relaxed Order.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324 Original-BUG=None Original-TEST=Modify settings, build and update the image to Samus and Original-check the settings are applied to Registers. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f Original-Reviewed-on: https://chromium-review.googlesource.com/219073 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31 Reviewed-on: http://review.coreboot.org/9206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02samus: Ensure PD controller is in RO mode for recoveryDuncan Laurie
In order to not break FAFT, and to have a quicker recovery mode boot, reboot the PD controller into RO image in romstage. This is done before the EC since rebooting the EC into RO will also reboot the host. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot samus EVT into recovery with 'dut-control power_state:rec' and ensure that the PD controller is rebooted to RO in romstage. Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add support for v3 commands on LPCDuncan Laurie
In order to talk to the PD controller with a passthru command coreboot needs to be able to use v3 commands. The command version is automatically detected based on the advertized flags from the EC. BUG=chrome-os-partner:30079 BRANCH=none TEST=boot on samus EVT Change-Id: I032eb185d80d5b68c82609910045e21d4521afcc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4f664b22645f0def87a73e9255297b3edccf436e Original-Change-Id: I94ace7741c9cd592921625fb793787247a5ca2aa Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218902 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Add commands to check PD image typeDuncan Laurie
Coreboot needs to be able to reboot the PD controller into RO image in recovery mode early in the boot process in order to avoid a lengthy recovery mode boot if it is only done at vboot software sync time. In order to do this a new device index field is added to the command structure which must be initaalized to zero for all EC transactions. This early init and image check code is only used in romstage so include it in the __PRE_RAM__ block. BUG=chrome-os-partner:30079 BRANCH=none TEST=build and boot on samus EVT in recovery mode and see that the PD is rebooted to RO mode early in the boot. Change-Id: Iee60aae4d49b83b4a377b71e41e8109858a90223 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b36cf37d9b5a7053ecbd15c748eac84836d413e1 Original-Change-Id: Iebc48709b527d3571618da775c849e1c3fcd6384 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeec: Update ec_commands.h from EC repositoryDuncan Laurie
This latest version includes PD passthru support. BUG=chrome-os-partner:30079 BRANCH=None TEST=build and boot on samus Change-Id: Ie718b73a6b125a863ae28e63769dd54edc267f0b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fbca0743a4b45828a466d05afc3a2e94d2e3da2e Original-Change-Id: I79d160219564155008f6231fec35808d1fbd6f04 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218901 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9202 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPUKein Yuan
Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands for these processors. Pre-conversion materials are compatible with USB PLL VCO current increase. Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL VCO current. BUG=chrome-os-partner:31199 TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register has new value. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bc01a3df80f5bd7fd86047c8bbf1584d19363e3b Original-Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0 Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211337 Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d) Original-Reviewed-on: https://chromium-review.googlesource.com/205970 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217772 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I1c825992a2b4dfac86f77cde567d2471ca4c19e6 Reviewed-on: http://review.coreboot.org/9200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Update PCIe configuration to follow BWGKane Chen
According to BIOS spec 8.14 B0:D28:F0[5:4] should be set to 11 BRANCH=none BUG=chrome-os-partner:28234 TEST=build ok, boot to Auron and Samus make sure register is set and PCIE is working Change-Id: I4a7e990993c230dfc1ba83ea75f56757c2c18e46 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 82826e3c44c26252697677ec08b95a8f174bc360 Original-Change-Id: I7c37245053ceae460dac0f18363f585244db72f8 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217414 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02chromeos: Add WiFi calibration CBMEM entry pointer to coreboot tableVadim Bendebury
This patch adds plumbing necessary to ensure that the CBMEM WiFi calibration blobs entry, if present, is referenced if the coreboot table. BRANCH=storm BUG=chrome-os-partner:32611 TEST=none - the entry is not yet in the CBMEM Change-Id: I072f2368b628440b6fe84f310eebc1ab945f809e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d0330280369753a6520196425e6dfc7d7bd226a3 Original-Change-Id: I04d52934ad1c5466d0d124b32df5ab17c0f59686 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225270 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9232 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Clear pending GPE events before entering sleep stateDuncan Laurie
In the case of an EC wake event that is pending but not cleared it is possible for the EC wake pin (i.e. GPIO27) to be asserted after the kernel triggers the sleep SMI but before the system goes to sleep. If this happens then the GPE will be reported as a wake source when the system wakes up again. BUG=chrome-os-partner:33218 BRANCH=samus,auron TEST=build and boot on samus, use the keyboard to enter suspend with suspend_stress_test and ensure that only the RTC is listed as a wake source upon resume. Change-Id: Id900132bb81e4cf50885a652ed00a142d951ea4d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 50396ab6a3a3efb3b3dea4f1c2a8f8804fed943e Original-Change-Id: I319dc22e21126a3086415f8f8b2b35eaec66fd50 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/225540 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9231 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Baytrail: Change PCIe root disable algorithmKenji Chen
Disable Root Port0 only when there is no PCIe device present on any root port. BUG=None TEST=Boot Rambi with PCIe installed/non-installed on RP0 to confirm the RP0 is correctly enabled/disabled. However, I still need someone to help check if RP0(no device) is still enabled if there is device on other RPs since since I have no devices having slots from RP1/2/3. Change-Id: Iae552975250ed6f309c423b847621b8994172891 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c5cef0b7c2c146f0d46ed49b75fd2ec8369210ce Original-Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7 Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217791 Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9219 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Baytrail: add _PRT to each PCIe root port deviceTed Kuo
Report PCI routing table of all PCIe root ports for legacy interrupt. Some PCIe devices using legacy interrupt can't work if PCI routing table isn't defined. It's necessary and defined in BWG Chapter 28.1.3. BUG=chrome-os-partner:31943 TEST=compiled and tested BRANCH=NONE Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: I2c684edfd1fc624bed471783584250cd9f5e66f5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b9040d564a32607327057a84b9aab14e66cd5b45 Original-Change-Id: Ia15ced6c5fdcc6712e5f2831e42c6dee320f166b Original-Reviewed-on: https://chromium-review.googlesource.com/218422 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Ted Kuo <tedkuo@ami.com.tw> Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw> Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw> Reviewed-on: http://review.coreboot.org/9201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02Samus: fix unused GPIO pinKenji Chen
Mark GPIO42 as unused according to Samus schematics BUG=None TEST=Make the chnage; Pass the build process; Need someone having the board perform the verification. Change-Id: Ib53a3ae062d414a2c98ec0756e759760d179e3fd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4e0f8f3276c575ff60fbda709de5d3cfe31a5900 Original-Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217344 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02ipq806x: provide soc specific CBMEM_CONSOLE_PRERAM_BASEVadim Bendebury
For now storm bootblock runs with DRAM fully initialized, this patch puts the early console between bootblock and rom phase. BUG=chrome-os-partner:31734 TEST=verified that preram_cbmem_console is set: $ grep preram_cbmem_console cbfs/fallback/bootblock.map 40618000 A preram_cbmem_console Change-Id: I2d63f5fde0d3794062068289c648d8bcda11a9a3 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6bdadad3787d6a4a2d4828b0f300455fedca2b8d Original-Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217291 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02smbios: add a family id in smbios type1 familyKane Chen
mosys will use this field to identify system BRANCH=none BUG=chromium:359155 TEST=build ok, use dmidecode to check whether data is written correctly Change-Id: I461215c012b6ad712b3f813a3928e90a23bf54f1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7adbdab761cd7b4bda0a43e7b1c4070de26f150a Original-Change-Id: Icfbd4c61fc49a9cb3d3ecd2b622339957963150c Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217400 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9230 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02vboot: add vbnv flash driverDaisuke Nojiri
this adds a driver for vboot to read and write nvdata in spi flash. it's assumed that flash contents are erased to 1-bits and write operations can only change 1-bits to 0-bits. when all nvram space is used, the driver will erase the whole block and start the next write from the beginning. BUG=chrome-os-partner:32774 BRANCH=ToT TEST=Built for cosmos. Change-Id: I40858f847151aa0770e1101e905476d270550f60 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 09713828b7b0cabd13a08de3f34e32bc4dbef4a4 Original-Change-Id: Ia9049f342b21fa4c289cb7b9254ab89ec1ef1699 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226525 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9229 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02broadwell: Add reporting of broadwell MCH revisionDuncan Laurie
Since the E0 and F0 stepping parts have the same CPUID it is necessary to use the MCH PCI device revision to determine what the actual stepping is. Add this decode table so the early output gives proper identification of the installed CPU type. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus with E0 and F0 parts Change-Id: Idce1e289cd958c77febc87395f27570247512a87 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a5346141e45b105a35a7641f60b29e02ab2bdfa3 Original-Change-Id: I1bc127badd75ecc34d3d2dbae5d272bd4d9f9082 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223158 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9228 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: Change CPUID 306D4 to report "E0 or F0"Duncan Laurie
The F0 stepping has the same CPUID as E0 stepping so report it as either stepping to avoid confusion. BUG=chrome-os-partner:32359 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I99a83855b4393d736724836b709702417483b5d2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 55ed3bc880c31c0ca5c8a21c335722af05eb57f7 Original-Change-Id: Ia4955f346ceb9be92e06ecea5b7a8fe2db84cabc Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9226 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02broadwell: me: Fix typo and add missing phase stateDuncan Laurie
Fix the typo of sate to state and add uKernel phase to just output the current state byte. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5f341ee6c58487aeb927cab0641742cb4071a6b7 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de6149508c50d0770fedfbe352e9149abea87b4c Original-Change-Id: I520a4cc75faffa5feeb6113ffd7b07a48c4e6f28 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222677 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02pinky: Enable EC_SOFTWARE_SYNCDavid Hendricks
CQ-DEPEND=CL:218766 BUG=none BRANCH=none TEST=built and booted on Pinky Change-Id: Ib3eed77553433e9f8c70af8b148729e628c95747 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 56b3e8c02a4e45653a5369ce47dcbce0c18f7194 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Icbee95350949bd9bfa4490a8a4b6bbf09beb4170 Original-Reviewed-on: https://chromium-review.googlesource.com/221019 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9224 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02mainboard/asus/kfsn4-dre: Set maximum installable memory to 64GBTimothy Pearson
Change-Id: I480d6bfe29c77119892fcb1fbb9779fd7e3529c3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9139 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-02northbridge/amd/amdfam10: Generate SMBIOS tables for RAMTimothy Pearson
TEST: Booted ASUS KFSN4-DRE and verified SMBIOS contents via dmidecode utility. Change-Id: Id656f2f6cf5a4ecafa03e150ad91f69107a4fe88 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-01mainboard/supermicro/h8qme_fam10: Fix indentations and spellingTimothy Pearson
Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9177 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01x86: set smbios rom size based on CONFIG_ROM_SIZEAaron Durbin
Instead of relying on the CBFS header's romsize field use the CONFIG_ROM_SIZE Kconfig variable. That value is what is used to create the rom file as it is. Therefore, just remove the dependency. Change-Id: If855d7378df20080061e27e4988e96aee233d1e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9130 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-01mainboards/amdfam10: Copy DIMM information to cbmem after romstageTimothy Pearson
src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info() function. Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-04-01mainboards: fix spd generationAaron Durbin
echo is evaluated by a shell builtin producing non-binary spd data of the form '-e -n \<byte>'. Correct this by using printf builtin which does the equivalent and is more cross platform friendly. Boards changed: gizmosphere/gizmo gizmosphere/gizmo2 google/bolt google/falco google/link google/peppy google/rambi google/samus google/slippy pcengines/apu1 Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9196 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-01cbfs: more accurate size check for simple buffer mappingDaisuke Nojiri
currently, if the cache size is, for example, 4096 byte, mapping 4096 byte data fails due to the overly strict check. this change allows cbfs_simple_buffer_map to use all the cache space to the last byte. BUG=None TEST=Booted Nyan Blaze. BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I0797b5010afd7316fdec605784e8f48e2d62c37f Original-Reviewed-on: https://chromium-review.googlesource.com/218883 Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b0b31da336fa2f87fe73f063782d6243f8262d10) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I15e11e574cd14484fe83c9c3674bb5c2d14422f6 Reviewed-on: http://review.coreboot.org/9178 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01northbridge/amd/amdfam10: Collect DIMM information for ramstage useTimothy Pearson
1.) Allow MCT information structures to be copied to cbmem. 2.) Retrieve DIMM vendor, model, and serial information. 3.) Allow maximum installable memory to be set via devicetree. Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9137 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-01northbridge/amd/amdmct: Pack MCT and DCT info structsTimothy Pearson
This allows safe access of romstage MCT values from ramstage Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9158 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi
And this path is already included properly elsewhere. Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9174 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01chromeos: INCLUDES was renamed to CPPFLAGS_commonPatrick Georgi
Change-Id: I39841c5358c53e6d2325d1304fd6cdfadb7f7ac4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9173 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
Some of the files which include cbfs_core.h don't even need the header definition while others just need the cbfs API which can be obtained from cbfs.h. Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9126 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31cbfs: add cbfs_serialized.h header fileAaron Durbin
The serialized format of CBFS is separate from the APIs used to traverse and read from CBFS. Separate those out so they can be consumed as a standalone header. Change-Id: I09f71d9c474ee9f23a62b0062ffa777963d1a4dd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9125 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31chromeec: Clear post code before reboot to RODuncan Laurie
When doing an EC requested reboot to RO mode clear the saved post code in order to prevent confusing events in the log where the system is rebooted intentionally. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus, run FAFT, check for odd eventlog entries about last post code 0x31 when it is rebooted during samus romstage entry point. Original-Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e32d7a7e54e7006b84509dbc2bfe9b4b022eba71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iad816669fb4054260f995f6f0bfb140121aaddff Reviewed-on: http://review.coreboot.org/9176 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-31program loading: provide one cache maintenance callbackAaron Durbin
Instead of having 2 different functions to call when a program is loaded provide a single callback with flags parameter. The previous callbacks for cache management routines did this: for_each_program_segment: arch_program_segment_loaded(start, size); arch_program_loaded(); Now, use one callback instead: for_each_program_segment: arch_segment_loaded(start, size, SEG_FINAL?); Change-Id: I3811cba92e3355d172f605e4444f053321b07a2a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-31payload loading: remove passing of struct payloadAaron Durbin
There's no need to keep track of struct payload within the boot state machine. It is completely contained within the payload loader module. Change-Id: I16fcecf43d7fb41fc311955fdb82eabbd5c96b11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8836 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-31loading: move ramstage cache function declarationsAaron Durbin
The functions related to caching ramstage were in cbfs.h. Now that the loading code is separate move those declarations to the common program_loading.h. Change-Id: Ib22ef8a9c66e1d2b53388bceb8386baa6302d28b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8835 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-31mips: don't open code romstage loadingAaron Durbin
Use the run_romstage() API to prevent code duplication and more maintenance for any API changes or features. Change-Id: I4122b813cccf4dc0703f256e1245deeeb90deeb9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9172 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-31cbfs: remove run_address()Aaron Durbin
The run_address() function is not used. Remove it. Change-Id: I96de4cf0a529b08943ff8281cedead642eb415de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9124 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-30google/veyron_pinky: Don't auto select CHROMEOSAaron Durbin
Indicate to reset of coreboot that MAINBOARD_HAS_CHROMEOS instead of auto-selecting it. Change-Id: Ide84bc0d8f801c79457dc05f768dd717a8a2f700 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9154 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30x86: fix SMM programs linked with gc-sectionsAaron Durbin
Commit f69a99db (coreboot: x86: enable gc-sections) added gc-sections to the linker command line. The SMM-specific linker scripts were not interrogated to see if all the sections were being included properly. .data, .bss, and .sbss did not have the proper globs set to put the SMM programs in the expected order. Lastly, explicitly set the ENTRY for the SMM programs. Change-Id: Ibb579d18d4819af666d6ec7dfc30776e8c404b71 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9160 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-30broadwell: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
When building HAVE_REFCODE_BLOB there are a couple of errors. One is a failure building !CHROME_OS. The other is from a header change where console_tx_byte() was declared. Change-Id: I4110debd6d3818d4a803ed22037166c226f2ed11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9142 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-30baytrail: fix HAVE_REFCODE_BLOB build errorsAaron Durbin
When building HAVE_REFCODE_BLOB there are a couple of errors. One is a failure building !CHROME_OS. The other is from a header change where console_tx_byte() was declared. Change-Id: Ia912902e8276d13b8e1716aa16c57b111579a03d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9141 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-30google/nyan_blaze: Don't auto select CHROMEOSAaron Durbin
Indicate to rest of coreboot that MAINBOARD_HAS_CHROMEOS instead of auto-selecting it. Change-Id: I61cde263f4ad7bd6758a61fc54c456c2ad2f343e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9153 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30Avoid 64bit math on MIPS platformsVadim Bendebury
Low level 64 bit division and modulo functions are not available for MIPS platforms, but are required by the printk formatter. Modify the code to avoid 64 bit math when building for MIPS. In case the user does print a value exceeding 2^32, send a few junk characters to the output to indicate a corrupted value printed. [pg: add the printed sequence to the comment, so git grep can find it] BRANCH=none BUG=none TEST=startup code on Urara properly prints CBFS address values which are passed as 64 bit integers. Change-Id: Ie777019cd8d55c53d5e816fbacfe79893c3d64c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8347f914a9cceca017668f8387ba679c2c79e66d Original-Change-Id: I25b8a900b3ba4ec1da3446dcc5f03101d5cdb757 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9162 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30mips: bring payload execution to current standardsPatrick Georgi
Change-Id: Id7f438a95fc7c7b41ce3d0fb419b0b455f8367a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9167 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30mips: fix write_tablePatrick Georgi
This replicates commit 3f7ad7b216b4021c7cb93201a94b0fae46f5e19e and commit 823edda98e6512d3f455b61549efea6fa68ee2b0 for mips. Change-Id: Id97e1fefa20cfa3bcb2cf0336b5a4ff7d9fe813b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30imgtec/pistachio: Bring uart driver to modern standardsPatrick Georgi
The console interface changed in upstream, and the driver didn't reflect that yet. This wasn't obvious because the driver wasn't compiled at all. Change-Id: Id18391e62e7ebd8f5fc929838ce27bf414e364f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/9165 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-30 19:35:47 +0000