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The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.
BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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D0 stepping with CPUID 0x60663 need to be added in coreboot.
TEST=Boot up with D0 stepping processor
Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Due to a schematic error, our code was written to configure more I2S0
pins than are actually used. We're also pinmuxing the whole bank of pins
over to the I2S controller even though we don't need them all. Restrict
the GPIO initialization and pinmuxing to the pins we really need so the
other ones can be correctly used as SKU ID pins on Scarlet.
Also, move the "audio" IO voltage domain selection to the other such
selections in the bootblock, since that covers two whole banks of GPIOs
and there's no guarantee that they're all used for audio (and thus not
needed before ramstage).
BUG=b:69373077
TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2.
Change-Id: I9314617e725fe83d254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
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These pins need to be pull-ups. I forgot.
BUG=b:69373077
Change-Id: I9314617e01d35898254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make lint-stable was giving an error on this.
Change-Id: I06d11d86151f683b82b6df537e3de8c52d33e8b4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.
Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.
Change-Id: I3bf691a0fb1f5c09e7b6c9965c9e506393ec31f6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adds Maxim98357a support for Nautilus using the generic driver
in drivers/generic/max98357
BUG=b:68686020
TEST=With entire merged audio should be enabled on max98357
speaker codec.
Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Nautilus board uses max989357a speaker codec and 4CH DMIC.
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on Speaker and captures on 4CH DMIC
Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Removes rs780_before_pci_init() since it was a no-op anyway.
Removes get_nb_rev() since this function is provided via a macro in
the header.
This Makes a lot of function non-static since the header has
prototypes for these.
Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.
BUG=b:70401101
TEST=Booted and noted only one lookup per stage.
Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES
BUG=b:65485690
TEST=Build & boot kahlee.
Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the spi header for spi function prototypes. Fixes spi.c build
error for the missing header.
Change-Id: I0dbb5bf84cc3462a7aa58a5531d6b8b8bc8ca4df
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This introduces a Kconfig option to include common Intel SPI code.
Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add proper variants gpio.h in dsdt.asl where the GPE_EC_WAKE and
EC_SCI_GPI is defined.
Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapted from Chromium commit d6655eb
[Skylake: create UPD Interface for acoustic noise tuning]
Add FSP 1.1 params needed for acoustic mitigation on google/caroline
(to be upstreamed in a subsequent commit).
TEST: build/boot google/caroline
Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Corrects MBSC/MBFS programming when initializing DRAM on boards with both
3 and 4 DIMM slots.
Reformats comments to current coreboot standards.
Drops some romcc "optimizations" no longer necessary.
Boot tested on asus/p2b-ls, where it fixes a memory related hang after
SeaBIOS resets the board with nothing to boot from.
Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Due to review 20b8c821e4 being abandoned and review 376dc82dca being
merged, file amd_pci_int_types.h became orphaned (not included by any
file), while an array similar to intr_types[] (but that also includes
the associated register index) was created in southbridge.c replacing
the original array functionality.
Remove the header amd_pci_int_types.h from the repository.
BUG=b:70328428
TEST=Build kahlee with no errors.
Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In the original Chromium source, PcdMemorySpdPtr is only set for
cyan, but none of the other Braswell variants. When upstreamed,
it was left set for all boards as it didn't appear to be problematic.
In wider testing, I came across one reks board for which it caused
FSP memory init to fail, so restricting the parameter to cyan only
as it was originally.
TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM,
observe board now successfully boots where it did not previously.
Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22782
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clean up and move UART related code under a single uart.c file.
Change-Id: I7eea910e065242689e87adac41281131674b39af
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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- The touchscreen interrupt was moved from the GPIO 3, as originally
suggested to GPIO 11. This changes the gevent from 2 to 18.
- Add EMMC reset on GPIO 93.
- Add EMMC bridge PCIe reset on GPIO 40.
- Set device enables to high.
- Remove extra SCI comment from GPIO 130.
- Set individual device PCIe reset pins to high.
- Enable global PCIe reset on GPIO 26.
- Mark LPC_CLK1 as unused.
- Update net names based on latest schematics.
- Set Direction and level/edge correctly for SCIs/SMIs.
- Remove SCI for pen detect.
- Add comments.
BUG=b:70234300, b:69681660, b:69305596
TEST=build grunt
Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on
PCIe port 1, so move the OemCustomize file into the variant directory.
- Add comments in baseboard version so it's easier to understand.
- Update reset pins, put the definitions in gpio.h
BUG=b:70255003
TEST=Build and boot Kahlee. Build Grunt.
Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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On GLK EC does not support temperature reads and does not control
the fans anymore, OS is responsible fan control through EC.
This hack enables running of the fan for boards without External EC.
Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Update FSP header files to match FSP v69_51.
UPD updates in FSP v69_51 are:
- SGX Epoch
- Sub/System Vendor ID
- Remove deprecated UPD
Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/22391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch does not put CLKRUN in IOSTANDBY.
Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add CNVi GPE in _PRW for wake on WLAN from S3
Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add GPE in _PRW for wake from S3 for HD-audio controller
Change-Id: I6ad289be8c58e48ad0ec9d2ee0894fe16b8f2e1c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This patch makes coreboot set the max current and voltage for barrel jack
adapters.
BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max current and
voltage are set as expected.
Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which
overrides the max input current and voltage when a barrel jack
adapter supplies power.
BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max
current and voltage are set as expected.
Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes
EC clear AP_OFF flag then hibernate.
This is needed to make Chromebox boot when cr50 toggles the EC's reset
line after TURN_UPDATE_ON command.
BUG=b:69721737
BRANCH=none
CQ-DEPEND=CL:802632
TEST=Verify Fizz reboot after cr50 update.
Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As noted on linux-pci, we have a weird way to handling "value" and
"scale" fields that are supposed to contain numerical values: we encode
them as a bitfield.
Instead define the two fields (offset and mask) and use numbers.
Another issue, not fixed in this CL, is that we write hard-coded values
while these fields really need to contain the max() of acceptable delays
of the downstream devices. That way the controller can decide whether or
not to enter a deeper power management state. It's noted as a TODO.
Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-on: https://review.coreboot.org/22740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Allow overriding specific GPIOs by SKU ID. Override two GPIO settings
for nasher to save the power consumption when the system in S0ix.
Change as below:
AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0.
AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0.
BUG=b:69025557
BRANCH=master
TEST=compile/verify the power consumption change from ~150mW to ~100mW
on clamshell SKU and from ~200mW to ~100mW for convertible SKU.
Change-Id: I9e0674f206426fddb3947273754774b310106334
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch ensures that all required information for pch/mch/igd
deviceid and revision are available in single stage and makes
use of local references.
TEST=Build and boot cannonlake_rvp to get PCH information as below
PCH: device id xxxx (rev xx) is Cannonlake-Y Premium
Change-Id: I420e94043145e8a5adcf8bb51239657891915d84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch ensures that all required information for
pch/mch/igd deviceid and revision available in single
stage and make use of local references.
TEST=Build and boot soraka/eve
Change-Id: I6f7f219536831210750a486ee3b3308d6f285451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22756
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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PCI resources MMIO space/bus master enabling is handled inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.
TEST=lspci from kernel console shows same pci device list
without and without this patch.
Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We only need the apu firmware in the RO region when building
for ChromeOS. Adding it to the RW regions is a waste of space.
BUG=b:70027919
TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections.
Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Skip LPC related gpio configuration if eSPI config option
is selected.
Change-Id: I15c5f769f36a1801217b1e3650379c7b181d814f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22757
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All preparation done, early_setup.c now useless. Delete early_setup.c,
BUG=b:64033893
TEST=None.
Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22569
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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With the old timing, the hblank time isn't large enough,
it may cause display artifacts. So fix it.
BUG=b:70160653
TEST=panel work on Scarlet rev2 board
Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This logical device is disabled in OEM BIOS. Disable here to match,
since its support is currently incomplete anyway.
Change-Id: I5c07136ec6a14a8ee8cb68537a2663b78fc0fa20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Updates ACPI tables with work done for asus/p2b-ls, including super I/O
related declarations.
Change-Id: Id2420da4ab04aa5f59ac0aa237d21477a03b826e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add ACPI tables support that will be needed for soft-off and S3 resume in the future.
Boot tested for soft-off.
Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Rework ACPI tables based on a mix of previous work on asus/p2b,
other boards in tree with better ACPI support, and OEM BIOS.
To be pulled in by DSDTs of mainboards using this southbridge.
Disable on-the-fly generation of mainboard _CRS node. It is not working
as it should and causes runtime errors when booting Linux. This node
to be included in mainboard DSDTs in followup patches.
Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In preparation to deleting early_setup,c, change early_ec_init() to use new
southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>.
BUG=b:64033893
TEST=Build, boot and check serial output, search for "Covered by wideIO xx",
which should match earlier message "Range assigned to wide IO xx" generated
within modified early_ec_init().
Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the new wide IO functions from southbridge.c to simplify code in
functions set_child_resource and lpc_enable_childrens_resources.
BUG=b:64033893
TEST=Boot to OS, check serial output against previously recorded serial
output from an image without all 5 related changes.
Change-Id: I8533e8ff766df8a8261298559aace7666487826d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create new generic wide IO functions in southbridge.c. These new
functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c.
BUG=b:64033893
TEST=Just build at this stage, full boot to OS and verify serial output
at related change 14fdd03a83. Some extra outputs for testing removed
when code was committed.
Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change adds variant nami derived from baseboard poppy.
BUG=b:70160119
Change-Id: Ic6795d49d3e6e98a32f4af0b621e8bb463041412
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change updates memory SPD handling code in baseboard poppy to
allow variants to define either LPDDR3 or DDR4 memory types. In
addition to that, it also updates the function to print SPD info
considering offsets that might be different across the two memory
types.
BUG=b:70188937
Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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