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2018-08-20nb/intel/raminit: Remove unused headersPatrick Rudolph
Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-20nb/intel/sandybridge/raminit: Fix DIMM type mappingPatrick Rudolph
The DIMM type read from SPD needs to be converted to make sure SMBIOS fills in the correct formfactor. Tested on Lenovo T430: The Form Factor no longer reads as unknown. Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph
Fill in SMBIOS type 17 DIMM serial number, read from SPD. Fixes FWTS SMBIOS type 17 test. Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20intel/common/block: Fix issues found by klockworkJohn Zhao
src/soc/intel/common/block/cpu/mp_init.c Function init_cpus: Pointer dev checked for NULL may be dereferenced. src/soc/intel/common/block/graphics/graphics.c Function graphics_get_bar: Pointer dev returned from call may be NULL and will be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20mb/kontron/ktqm77: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: Ib5799cceacefa89385a7615ef1c4b4d06157044f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20ec/lenovo/pmh7: use read/write function in clear_bit/set_bitAlexander Couzens
Make the code simpler and improve readability. Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20src/drivers/usb/Kconfig: increase warning signs for BBB ownersStefan Tauner
The help text is already very clear but some users (first and foremost the author of this patch ;) are still selecting USBDEBUG_DONGLE_BEAGLEBONE when using a BeagleBone Black and waste hours on analyzing the debug output of EHCI debug driver. Change-Id: Ibf002db7d81ed44878f3ce0324170e4b99e780a5 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-19google/cyan: Fix ACPI resource scope for Melfas touchscreenMatt DeVillier
Fix scope of ResourceSource, which should match the scope of the device itself. Change-Id: I9d0ff0ecc2721ec55b1ed12dddb495cd55966daf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-19mb/lenovo/x1_carbon_gen1: add support for hynix memoryAlexander Couzens
All different memory configuration should be supported by now. Thanks to Igor Lee. Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17arm64: Factor out common parts of romstage execution flowJulius Werner
The romstage main() entry point on arm64 boards is usually in mainboard code, but there are a handful of lines that are always needed in there and not really mainboard specific (or chipset specific). We keep arguing every once in a while that this isn't ideal, so rather than arguing any longer let's just fix it. This patch moves the main() function into arch code with callbacks that the platform can hook into. (This approach can probably be expanded onto other architectures, so when that happens this file should move into src/lib.) Tested on Cheza and Kevin. I think the approach is straight-forward enough that we can take this without testing every board. (Note that in a few cases, this delays some platform-specific calls until after console_init() and exception_init()... since these functions don't really take that long, especially if there is no serial console configured, I don't expect this to cause any issues.) Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17sandybridge/raminit_common.c: fix printram statementIru Cai
Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/28117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17soc/amd/common/block/pi/agesawarapper.c: Use find_image()Richard Spiegel
In preparation to removing AmdLib, replace function LibAmdLocateImage() with its ported version find_image(). BUG=b:112625809 TEST=Build and boot grunt. Change-Id: I75ddd55f7e3e7f2cd7914f97c99b62690ae70660 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28164 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17soc/amd/common/block: Port vendorcode's LibAmdLocateImageRichard Spiegel
In preparation to removing AmdLib, function LibAmdLocateImage() has to be ported to be used by agesawrapper. The most important aspect of this porting is that it has to obey coreboot format, specifically 8 character tab and 80 characters max. This required breaking the function in 2 (to solve indentation) and rename some variables to shorter names. One important aspect was breaking (AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset) into: image_ptr = (AMD_IMAGE_HEADER *) current_ptr; if (validate_image((void *)image_ptr->ModuleInfoOffset, and, within validate_image completed by: AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain; BUG=b:112625809 TEST=Build grunt, functionality tested in next commit. Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17google/grunt: Update TP/TS/H1 i2c timingsKevin Chiu
After adjustment on Careena EVT TP: 400.0 KHz TS: 396.8 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28119 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17x86/acpigen: Fix ACPI _ROM methodMarc Jones
Fix the following Error: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 142 Line | AML source -------------------------------------------------------------------------------- 00139| 00140| Scope (\_SB.PCI0.IGFX) 00141| { 00142| Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00143| { 00144| OperationRegion (ROMS, SystemMemory, 0xCD520000, 0xFE00) 00145| Field (ROMS, AnyAcc, NoLock, Preserve) ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. Use the acpigen_write_method_serialized() to correct the error. BUG=b:112476331 TEST=Run FWTS. Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-17ec/google/chromeec: Fix ACPI FWTS errorMarc Jones
Fix the following FWTS error: FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line 3038 Line | AML source -------------------------------------------------------------------------------- 03035| Return (One) 03036| } 03037| 03038| Method (_Q09, 0, NotSerialized) // _Qxx: EC Query | ^ | Warning 3115: Not all control paths return a value (_Q09) 03039| { 03040| If (Acquire (PATM, 0x03E8)) 03041| { ================================================================================ ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths do not return a value. All control paths that return must return a value otherwise unexpected behaviour may occur. This error occurs because a branch on an conditional op-code returns a value and another does not, which is inconsistent behaviour. _Q09 is a reserved method and can't return a value. Change the logic so that no return is used and avoid this test error. BUG=b:112476331 TEST=Run FWTS. Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-17mainboard/google/kahlee: Fix ACPI method Not Serialized errorMarc Jones
Fix the following failure from FWTS: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 131 Line | AML source -------------------------------------------------------------------------------- 00128| } 00129| } 00130| }) 00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00132| { 00133| Name (RBUF, ResourceTemplate () 00134| { ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. BUG=b:112476331 TEST= Run FWTS. Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28122 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17Fix PCI ACPI _OSC methodsMarc Jones
Fix the IASL build warnings: Object is not referenced (Name [CDW2] is within a method [_OSC]) Object is not referenced (Name [CDW3] is within a method [_OSC]) Remove the not referenced objects. They are not needed. BUG=b:112476331 TEST=IASL doesn't give the warning. Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17src/include: add more msr definesMatt Delco
This change adds some MSRs that are needed in a subsequent change to add support for Continuous Performance Control. Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-17arch/x86/acpigen: add methods for cppcMatt Delco
This change adds 2 methods for Conginuous Performance Control that was added in ACPI 5.0 and expanded twice in later versions. One function will create a global table based on a provided struct, while the other function is used to add a _CPC method in each processor object. Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-17superio/ite/it8720f: fix power control initFelix Held
The existing code for modifying the power state after power loss of the system only implemented the transitions from power off to either power on or power keep properly. Since I don't have a board with this chip, I couldn't test the patch on real hardware. The two cases described above were tested before the original patch was merged, so I'd expect this to work. Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17mb/intel/coffeelake_rvp: Update spd details as per Coffeelake boardMaulik V Vaghela
Update SPD details to match with Coffeelake U RVP board BUG=none BRANCH=none TEST=Boot on coffelake U rvp board and check if memory training is passing and board boots till payload. Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-17mb/intel/coffeelake_rvp: Update GPIO table for Coffeelake U RVPMaulik V Vaghela
Update GPIO table as per board schematics. GPIO table for other variants will be added later. Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-17Nami: Disable powering off EC on cr50 updateDaisuke Nojiri
Nami doesn't support wakeup from hibernation by CR50. This causes the device to remain turned off after CR50 update. This patch disables turning off EC on cr50 update. CR50 resets the whole system. So, EC reset is not required. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:112604277 BRANCH=none TEST=gsctool -a -u /media/removable/cr50.bin && reboot Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update' then reboots. Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709 Reviewed-on: https://review.coreboot.org/28113 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17cr50: Allow boards to disable powering off EC on cr50 updateDaisuke Nojiri
This patch allows boards to disable turning off EC on cr50 update. If CR50 resets the whole system, an EC reset is not required. BUG=b:112604277 BRANCH=none TEST=gsctool -a -u /media/removable/cr50.bin && reboot Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update' then reboots. Change-Id: I60a7aa50a549e7a5a1a114245fbf7b9646d813bb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/28110 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17intel/socket_mPGA604: Keep only model f2xKyösti Mälkki
The only board left in the tree (aopen/dxplplusu) with this socket is the slower of the mPGA604 variants with FSB 533. Change-Id: I04707a0dcb8f5b6235ead8c02ddfddfe7c3b8b1b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/28116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-17soc/intel/skylake: permit Kconfig to set subsystem IDMatt Delco
This change permits the subsystem ID to be specified via Kconfig for the devices on the SoC. Some devices are getting zero'ed subsystem IDs because the unset (and thus zero'ed) config options are overwriting the fsp defaults. With this change the fsp defaults will only be overwritten by non-zero config values. Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-17src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headersRichard Spiegel
Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed. BUG=b:112602580 TEST=Build grunt and gardenia. Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28093 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-16src/{commonlib,lib}: Fix typoElyes HAOUAS
Change-Id: If7650ac4d9be2614a9665c7f2aba9ac5cc413efe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-16mb/*/*/cmos.default: Harmonise CMOS files syntaxElyes HAOUAS
These files are being updated to match the prevailing style of cmos.default files. Change-Id: I47d31d6fec8c9eb856aed0c63824d9556b7705e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-16google/grunt/aleena: Update Raydium TS device ACPI nodesTim Chen
change I2C irq to EDGE trigger BUG=b:112616824 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: I86ec32bb3f2626e65d76c3259e3c4244a970e5de Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-16sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5Stefan Tauner
The specification updates for ICH 9 & 10 require to leave the register in its default state by reserving all of its bits. Writing to it does not seem to make a difference anyway since reading it afterwards does not reflect the write (tested on ICH10). Therefore we should omit the writes but document this fact in the code because it is easy to miss from the datasheet alone. Change-Id: Iec0d79f926a826a80b90907f7861d0cb2ca30a5b Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-08-16amd/stoneyridge: Add PMxC0 reset status to boot logEdward Hill
Print the PMxC0 S5/Reset status bits to the console. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-15mb/*/*/cmos.default: Decrease debug_level to 'Debug'Elyes HAOUAS
Used default console log level is 7 in src/console/Kconfig. So let cmos.default use the same level as default. Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15arch/x86/acpigen: refactor calls to acpigen_write_registerMatt Delco
All of the callers to acpigen_write_register() also make calls to acpigen_write_resourcetemplate_[header|footer](). This change introduces acpigen_write_register_resource() to unify all of those trio of calls into one. I also made the input parameter const. Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27672 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15Stoneyridge: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal of VENDORCODE_FULL_SUPPORT from coreboot. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/binaryPI/AGESA.c: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Id91e76282509743070e34c02082d3f3f46a14059 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file: vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from files FchLib.c and FchPeLib.c. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Lib: Remove read modify write functionsRichard Spiegel
Now that the functions that used them were safely removed, remove LibAmdIoRMW(), LibAmdMemRMW() and LibAmdPciRMW(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW()Richard Spiegel
The functions that use LibAmdPciRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdPciRMW() itself. The functions to be removed are: From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c: ProgramPciByteTable(). From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(), RwXhci0IndReg() and RwXhci1IndReg(). From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00: Remove functions that use LibAmdMemRMW()Richard Spiegel
The functions that use LibAmdMemRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdMemRMW() itself. The functions to be removed are: ProgramFchAcpiMmioTbl() and GetEfuseStatus(), both from vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c. BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15google/grunt: Remove BayHub EMMC driving strength overrideKevin Chiu
Side effect was observed that after override BayHub EMMC driving strength to the max, EMMC CLK will be reduced to 51.x Mhz from 200 Mhz. This will cause OS installation fail on Samsung EMMC sku. BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15mb/google/poppy/variants/nocturne: remove dup'ed dptf_enableMatt Delco
This file contains two instances of "dptf_enable" = "1". This change removes the 2nd instance (it doesn't have an explicit comment like the 1st instance). The dptf devices still seem to be present even with this change, as expected. Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15mb/google/poppy/variants/nocturne: sx9310 to 400kbMatt Delco
The spec of the sx9310 says the I2C interface can handle standard (100kb/s) and fast mode (400kb/s). The current setting is using fast plus (1000kb/s) so this change is reducing the speed to fast mode. I've been using the sensors with this change for a few weeks now, though I also don't recall seeing an issue prior to this change. Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"Caveh Jalali
This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4. Camera power is now handled by ACPI rules - no need to force the GPIOs on by default. BUG=b:80106316,b:111141128 Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28072 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/atlas: Add DISPLAY_DCR_EN GPIO pinCaveh Jalali
This defines new GPIO pin for controlling the display panel CABC function. The default value is high (enabled). BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28070 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/atlas: Update DPTF sensor namesCaveh Jalali
This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 TEST=verified new strings show up in /sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28069 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 01:31:26 +0000