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2019-06-08mb/lenovo/t430: Fix Dual GraphicsPatrick Rudolph
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix disabling iGPU in 'Dual Graphics' on Lenovo T430. * Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select DRIVERS_LENOVO_HYBRID_GRAPHICS. Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-08nb/intel/sandybridge: Drop iommu.c and rename functionsPatrick Rudolph
* Move the contents of iommu.c to early_init.c. * Name the functions like done in intel/soc/common. * Move PAMx register setup to own function Preparations for integration in soc/intel/common/* Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I3ec395bf6722bceb84316e92733dcfcd7a093639 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32068 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/acpi: Remove Return for PS0/3Christian Walter
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements. Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/bootblock: Add SPT C236 to PCH TableChristian Walter
Add Skylake C236 to the PCH Table. The one which was already in there is actually the CM236 and not the C236. This can be checked in datasheet: 100-series-chipset-datasheet-vol-1 p. 25. Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-08northbridge/gm45: document that raminit doesn't support mirrored ranksFelix Held
Change-Id: I8a66a1355974f6771c5e4bae0dc60da2447122d1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-07sb/amd/sb700: Fix misleading formattingMarshall Dawson
Change-Id: I65872d6f1d71d050c8589d3616340648cf95048b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-07ec/google/wilco: Add UCSI supportDuncan Laurie
This change adds support for the UCSI specification in order to provide information about the Type-C port and an interface to perform power and data role swap. This change is split across the DSDT and SSDT, with the shared memory and operation region declared in the SSDT after being allocated in CBMEM. The OS will fill in the registers in the system memory region and then call the _DSM method wtih a read or write argument. The DSM method will copy the required registers to/from the system memory and the EC and perform the write or read action. Responses from the EC will generate a new SCI with event code 0x79 which will notify this UCSI ACPI device and the OS driver will take action to read status from the EC. BUG=b:131083691 Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07cbmem: Add ID for UCSIDuncan Laurie
The USB Type-C Connector System Software Interface (UCSI) defines a required memory oregion for the OS UCSI driver to use to communicate with the BIOS and EC. This provides a CBMEM ID that can be used by drivers to allocate this shared memory region for the UCSI driver to use. BUG=b:131083691 Change-Id: Id5b7fa19436443bc11a6ebe3ce89cd552cee4d85 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07soc/intel/cannonlake: Add _DSM method for SD controllerV Sowmya
The SD controller seems to take some time after restarting the clock at 1.8V before it actually switches from 3.3V to 1.8V. Add a _DSM method that simply sleeps when switching between 3.3V and 1.8V. Otherwise, the kernel times out too quickly waiting for the card to acknowledge the 1.8V switch. The card itself is waiting until it sees the clk signal being driven at 1.8V. BUG=b:125441242 TEST=Boot Hatch with SD card and CR2 removed, observe voltage switch succeeds. Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Signef-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07soc/intel: Add some missing MCH PCIe IDsKeno Fischer
These are documented in the Intel Datasheet entitled "6th Generation Intel® Processor Datasheet for S-Platforms" "6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2) Without them, coreboot fails to properly inform the payload of the amount of available memory. Signed-off-by: Keno Fischer <keno@juliacomputing.com> Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-06mb/google: Add GPU panel settings for SKL/KBL boardsNico Huber
The values are generated from the respective VBTs. Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30247 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/intel/skl/graphics: Implement panel setupNico Huber
Logs from Linux' i915 suggest that not even the FSP/GOP takes proper care of this. The sequence is mostly the same as on older platforms, with a slightly different configuration of the backlight PWM. We light the panel up with 50% PWM duty cycle. This often results in an already rather high perceived brightness, but shouldn't be too blinding. Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-06soc/amd/common: Make biosram functions more readableMarshall Dawson
Modify the 16 and 32 bit BIOS RAM access functions that had been originally moved from stoneyridge. This was suggested in the review of 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: I5b491da6f263cbab2b549301e16a7e19896f2428 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32932 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Update AcpiMmio commentsMarshall Dawson
Document the AcpiMmio individual blocks better. This is in response to a request in gerrit for 69486cac7: Create AcpiMmio functionality from stoneyridge Correct comments that were inadvertently left in place from older patches. Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06qcs405: Enable VBOOT_MIGRATE_WORKING_DATANitheesh Sekar
Enable VBOOT MIGRATE_WORKING_DATA so that the data required by depthcharge is copied into the coreboot tables and made available to depthcharge after BOOT_IMEM is cleansed. Change-Id: I0317b73d24b07553672695998589f86677e0be64 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-06qcs405: Add PRESERVE flag for RO_VPDNitheesh Sekar
Add PRESERVE flag to preserve the VPD data. Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33020 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Fix consistency in AcpiMmio argumentsMarshall Dawson
Change all arguments named "offset" to "reg" to match the others. These should have gone into change 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32930 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Clean up prototypes for AcpiMmioMarshall Dawson
Reorder the biosram prototypes to match the rest of the file. Remove prototypes for asf 32-bit functions that have not been implemented. Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32929 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/amd/stoneyridge: Move alink source to commonMarshall Dawson
Relocate the alink access functions out of stoneyridge where they were dead code. This source maintains the ability to access all register spaces, however more modern APUs define only ABCFG in the BKDGs. BUG=b:131682806 Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Add ALink-AHB Bridge to iomap.hMarshall Dawson
Add the address and replace the hardcoded value in the ASL code. Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32662 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move sata to commonMarshall Dawson
Relocate generic sata support from stoneyridge to common/block. BUG=b:131682806 Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32661 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Split sata functionalityMarshall Dawson
Separate chipset-specific source from sata_init(), and modify it to better match coreboot conventions. A subsequent patch will move the generic portion to soc/amd/common. The support for enabling port multipliers appears to have been first added for Kabini. Although missing from the documentation, the ability to affect the HBA Capabilities Register seems to remain for Stoney Ridge. Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Remove sb_util.cMarshall Dawson
Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk(). Relocate the remaining functions to get/save UMA information to southbridge.c. Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06nb/intel/pineview/raminit.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I4faf698e904c461803e867d212c31958119cc0ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Relocate acpi_get_sleep_type()Marshall Dawson
Move the function into common code. Convert it to use the memory- mapped access type. Convert vboot_platform_is_resuming() to call it instead of duplicating the source. BUG=b:131682806 Change-Id: I245bebb8dc2d331cdd56acfb245a004536b792ab Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32658 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move IOMMU support to commonMarshall Dawson
BUG=b:131682806 Change-Id: Icb02180645c9e7e6dc973438c777228b031b3f54 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32657 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move hda.c to commonMarshall Dawson
BUG=b:131682806 Change-Id: I1aa869584fd6743101c07a6a508abff6426df18d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32656 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Relocate MMIO access of ACPI registersMarshall Dawson
The AcpiMmio block allowing direct access to the ACPI registers has remained consistent across AMD models. Move the support from soc//stoneyridge to soc//common. BUG=b:131682806 Change-Id: I0e017a71f8efb4b614986cb327de398644599853 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Rework block/acpiMarshall Dawson
The halt.c file relies on the ACPI register block in the AcpiMmio range. This register block is consistent across AMD device generations, so to prepare for moving additional stoneyridge support to this directory by changing the file name and add a Kconfig symbol to control the build. BUG=b:131682806 Change-Id: I2f7442dd78bced7f69b0416a8cd751291f82151f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32654 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move LPC support to commonMarshall Dawson
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Rework SPI base address get/setMarshall Dawson
A subsequent patch will move the soc//stoneyridge LPC functionality to a common directory. Prepare by reworking the SPI BAR configuration function in southbridge.h. The SPI BAR is not a typical PCI BAR, and is at D14F3xA0. Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move GPIO support to commonMarshall Dawson
The banked GPIO functionality in the AcpiMmio block has been consistent since the Mullins product. Move the basic support into a common directory. Each product's pin availability, MUXes, and other details must remain specific to the product. The relocated source also drops the weak configure_gevent_smi() that reports SMI is not available. The stoneyridge port relies on SMI to do its initialization, similar to modern soc/intel devices. This is the plan for future soc/amd ports, so make a missing function a build error instead of a runtime warning. BUG=b:131682806 Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-06Makefile.inc: Compile smm files independent ARCH_RAMSTAGE_X86_32/64Subrata Banik
This patch makes smm related files compile independent of ramstage getting compiled. If user selects RAMPAYLOAD to boot without ramstage, there will be need for smm code to get compiled independently. Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06sb/intel/ibexpeak: Copy the sandybridge bootblock.c fileArthur Heymans
This allows to port C_ENVIRONMENT_BOOTBLOCK to sandybridge separately from nehalem. Change-Id: If3c6619cf22d1e2995eb19823b0f3f969d252b3b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-06mb/hp: Add Z220 SFF workstationPatrick Rudolph
* Add initial board commit based on HP8200 SFF. * Add documentation. * Serial and PCIe slot are working. Tested on HP Z220. Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/soc/intel/common/smbios: Add addtional infos to dimm_infoChristian Walter
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry. Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06siemens/mc_apl5: Add own GPIO tableMario Scheithauer
Because of some differences to the baseboard this board variant needs its own GPIO table. Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-06sb/intel/i82801gx: Detect if the southbridge supports AHCIArthur Heymans
This automatically detects whether the southbridge supports AHCI. If AHCI support is selected it will be used unless "sata_no_ahci" is set in the devicetree to override the behavior. Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-05mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOSShelley Chen
The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-05coreboot: Add i2c clock API for qcs405Taniya Das
Add support of i2c clock enable, disable and configure API. Change-Id: Ia0b42357ac09bf0ab60aad18c44e5ef27fe9dac3 Signed-off-by: Shefali Jain <shefjain@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32545 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outwHannah Williams
outw takes (value, addr) not (addr, value) Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams <hannah.williams@dell.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-05mainboard/facebook/fbg1701: Do initial mainboard commitFrans Hendriks
Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-05lib/Makefile.inc: Add hexdump.c to postcar stageFrans Hendriks
hexdump() is not available in postcar stage. Add hexdump() functionality to postcar stage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Change-Id: Ibdce911065c01b0a1aa81dc248557257d0e420b0 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-06-05src/drivers/intel: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer fih as FORWARD_NULL. Add sanity check for fih to prevent NULL pointer dereference. BUG=CID 1401717 TEST=Built and boot up to kernel. Change-Id: Ia6853e5302c87d9ffe52b942f067be56f6e77406 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-05nb/intel/x4x: Remove variable set but not usedElyes HAOUAS
Change-Id: I142ae6f7806b3f57b98a158e8f26592aed8fa452 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32939 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05src/arch/x86: Prevent attack on null pointer dereferenceJohn Zhao
Clang Static Analyzer version 8.0.0 detects null pointer argument in call to memory copy function. Add sanity check for pointer header to prevent null pointer dereference. TEST=Built and boot up to kernel. Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-05sb/intel/i82801gx: Include chip.h directlyArthur Heymans
Change-Id: I3d743e90444292be687999ab4f50aa89d514fbad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33171 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05mb/*/devicetree.cb: Remove unavailable PCIe portsArthur Heymans
Some variants only support 4 PCIe ports so there is no need to have those unavailable ports in the devicetree. Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04mb/google/sarien: Fix SSD's power off sequence before going to S5Roy Mingi Park
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04qcs405: Add SPI driver supportPrudhvi Yarlagadda
Add SPI driver support in coreboot. Change-Id: I813ba0b5cc8344c463c3e41ff6db80bc0d8ebd96 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32058 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 08:54:57 +0000