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2020-01-18soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDsGaggery Tsai
This patch adds CML-S 2 and 4-Core MCH IDs and fix wrong ID for 10-Core ID. Change-Id: I30f6c8a5234b7754d984b598bf7bae103ec9712e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18google/eve: tweak VBT settingsMatt DeVillier
- Disable Windows driver DPST function - Set POST resolution to 1800x1200 - Set POST brightness to 225 (0-255 scale) Test: Boot Windows on EVE, verify display backlight control functional and no lock ups from switching in/out of tablet mode. Change-Id: Ida64a44df2449f1ff0dc5c8d0ec7b40a183566a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mainboard/google/puff: update SATA strengthTim Chen
Base on SATA SI report to fine tune the strength for port 1. BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine. Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18soc/intel/cannonlake: Add chip config for SATA strengthJamie Chen
Add config to chip.h for tuning SATA gen3 strength. BUG=b:147351936 BRANCH=none TEST=build successful in puff Change-Id: I4dcd23834fa3c01c1d88697a7bb8cf361709b62e Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38432 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18ec/google/wilco: Set minimum UCSI_ACPI region lengthBernardo Perez Priego
IMD provides support for small and large allocations. Region IMD Small memory is 1 KB with 32 Bytes alignment, this region holds smaller entries without having to reserve a whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with 4 KB alignment. The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached. Cache mapping is set on page boundaries and all IMD Small is within the same page. If another driver maps the memory as write-back before the UCSI driver is loaded then the UCSI driver will fail to map the memory as not cached. Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will now be located within its own page. This patch will force UCSI_ACPI region to be located in IMD Large region. BUG=b:144826008 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Id00e76dca240279773a95c8054831e05df390664 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update ACPI filesRavi Sarawadi
Add and update ACPI files for Tiger Lake SoC Use ASL2.0 code syntax for new acpi(camera_clock_ctl.asl) Reference PCH EDS#576591 vol1 rev1.2 PCH EDS#575857 vol2 rev1.0 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37781 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update pci dev definitionWonkyu Kim
This change updates pci dev definition according to TGL EDS. Add GSPI3 case in chip.c according to updated pci dev definitions. Reference TGL Process EDS#575681 rev1.0 TGL PCH EDS#576591 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4717ac3cc877b13978b18ada504740512f10c709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38341 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/facebook/monolith: Enable the xDCI controllerWim Vervoorn
Enable the VBOOT_ALWAYS_ALLOW_UDC option to actually enable the xDCI controller. BUG=N/A TEST=build Change-Id: Ib51f2c82e69db83cebceb71ba5f1305764e0feca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18security/vboot: Allow UDC regardless of vboot stateWim Vervoorn
When a VBOOT enabled system is used without ChromeOS it may be valid to allow the UDC independent of the vboot state. Provide the option to always allow UDC when CHROMEOS is not selected. BUG=N/A TEST=build Change-Id: I6142c4a74ca6930457b16f62f32e1199b8baaff8 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18mb/intel/tglrvp: Update tglrvp_up3 devicetreeRavi Sarawadi
Update Tigerlake RVP UP3 devicetree to reflect devices used by tglrvp_up3. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common: Fix typosSridhar Siricilla
Fix typos and replace spaces with tab in macro definitions. TEST=Build and Boot hatch board Change-Id: I43b2df7defc97aaeb7c8c9dfbe08ce78ba81f39b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/common/cse: Add description for macrosSridhar Siricilla
Below changes are done in the patch: 1. Remove unnecessary lining, and replace spaces with tabs 2. Add description for macros 3. Correct comment mentioned for wrapper #ifndef TEST=Build and Boot hatch board Change-Id: I630446234321e7998ab42f8506a58b16e9ce4eb0 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/intel/jasperlake_rvp: Remove sd card detect gpioMaulik V Vaghela
Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is failing due to this. We will update correct gpio for sd card detect once we have Jasper Lake soc gpio patch. partner bug for tracking: https://ticket.coreboot.org/issues/251 BUG=None BRANCH=NONE TEST='jslrvp' mainboard builds successfully Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-18arch/x86/post.c: Hide cmos_post_code from SMM contextMaulik V Vaghela
Code in SMM segment using cmos_post_code will give compiler error since cmos_post_code function is not getting compiled during SMM stage. Also as per patch discussion, CMOS uses a split IO transaction and it's not really safe to call cmos_post_code from SMM context. Thus we'll hide the call for SMM context. Change-Id: Iffdcccaad48e7ad96e068d07046630fbe4297e65 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-18mb/opencellular/elgon: Fix typoElyes HAOUAS
Change-Id: I6724637c7333ae6be7ada3e8ebe878b2a1061dd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-18mb/amd/bettong: Fix typoElyes HAOUAS
Use 'irremovable' over 'unremovable' Change-Id: Id305dbe56a93740abc49d85d11402d1b63989dad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37527 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18src/include: Fix typosElyes HAOUAS
Change-Id: Ia8e6e5bd5ac2565263d81df8ca81d62436a3301f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18soc/intel/common/cse: Add consistent HECI command id/group id namingSridhar Siricilla
Below changes are done: 1. Consistent HECI command/group ID naming. 2. Rename macros to match with Intel ME BIOS Spec. 3. Move command ids, group ids and related macros into cse.h 4. Add description for structure members. TEST=Build and Boot hatch board. Change-Id: Ia902095483d5badf778d0c1faa6bf8cc431f0e50 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-18mainboard/google/puff: update USB configurationJamie Chen
Base on USB SI report to fine tune the strength and correct some OC pin settings. BRANCH=none BUG=b:147206010 TEST=build and test all usb ports function work fine. Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18console/post: NOPOST means NOPOSTPatrick Georgi
Not "NOPOST except when the board says something else". Change-Id: I3608e9c3a7d2338363a4320c8718b20ef25a038a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mb/google/link: drop dummy mainboard_post functionPatrick Georgi
It was never filled it, it probably never will be filled in, so stop the pretense. Change-Id: I7632b763b8518304d36a818ce262cc127f95b9f0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mb/facebook/monolith: Describe device 4.0 in devicetreeWim Vervoorn
BUG=N/A TEST=build Change-Id: Id7267aa6d4266bb7807fb3c25b5e2704c8d81df7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38430 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/{skylake,common}/acpi/dptf/thermal.asl: Prevent iasl remarksWim Vervoorn
Prevent iasl remarks about unused parameters. BUG=N/A TEST=build Change-Id: I54fa4712e618038fdd5a96c2012c2ec64ca34706 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/facebook/monolith: Add support to read cpu temperatureWim Vervoorn
Read the CPU temperature from the EC. For this board the EC support is limited to reading the CPU temperature sensor at this moment. Events are not supported. BUG=N/A TEST=tested on facebook monolith using acpidbg The TSR0._TMP method is returning the correct values. Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18cbfs: Remove locator conceptJulius Werner
When vboot was first integrated into CBFS it was still part of Google vendorcode. So to not directly tie custom vendorcode into the core CBFS library, the concept of cbfs_locator was introduced to decouple core code from an arbitrary amount of platform-specific implementations that want to decide where the CBFS can be found. Nowadays vboot is a core coreboot feature itself, and the locator concept isn't used by anything else anymore. This patch simplifies the code by removing it and just calling vboot from the CBFS library directly. That should make it easier to more closely integrate vboot into CBFS in the future. Change-Id: I7b9112adc7b53aa218c58b8cb5c85982dcc1dbc0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18intel/apollolake: Remove CBFS locator overrideJulius Werner
This patch removes the CBFS locator override for the Apollolake SoC and instead integrates the extra sanity check it was used for straight in the boot device initializer. Change-Id: Iccdb885be233bb027a6a1f2cc79054582cbdf3fc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-18mb/facebook/monolith: Update power supply settingsWim Vervoorn
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies according to the information in the schematic. The IccMax for these supplies is lower than the standard supported by the SoC. BUG=N/A TEST=build Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mainboard/puff: Fix ACPI tables to advertise correct featuresEdward O'Callaghan
Provide Puff with it's own copy of ec.h copied from the baseboard/includes however with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. V.2: drop EC_ENABLE_ALS_DEVICE as well. V.3: set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. V.4: drop EC_HOST_EVENT_MODE_CHANGE && provide wake pin for EC for _PRW WoL method V.5: drop EC_HOST_EVENT_KEY_PRESSED BUG=b:147850335 BRANCH=none TEST=builds Change-Id: If13bd124c7229ced996efb841980604d13be09af Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-17mb/tglrvp: update gpio pin mux for NVMeWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-17drivers/spi/spi_flash: organize spi flash by sector topologyAaron Durbin
By grouping the spi flash parts by their {vendor, sector topology} tuple one can use a common probe function for looking up the part instead of having per-vendor probe functions. Additionally, by grouping by the command set one can save more space as well. SST is the exception that requires after_probe() function to unlock the parts. 2KiB of savings in each of verstage, romstage, and ramstage on Aleena Chrome OS Build. Change-Id: I9cc20ca0f3d0a1b97154b000c95ff2e7e87f3375 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17drivers/spi/spi_flash: introduce common spi_flash_part_id objectAaron Durbin
To further drive to a common approach for describing the spi flash parts in the drivers add spi_flash_part_id object. All the drivers are updated to utilize the new object. Additionally, the driver_private is also not needed in the spi_flash object. A Chrome OS build of Aleena provides 960 byte saving of text. A subsequent patch will save more memory. Change-Id: I9c0cc75f188ac004ab647805b9551bf06a0c646b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-17drivers/spi/spi_flash: remove continuation byte supportAaron Durbin
There was code to handle the case of continuation bytes for identifying the manufacturer id to a jedec rdid command. However, all the parts that currently supported have this defined to be 0. Remove the unused continuation byte support. Change-Id: Ia7c63162e4ef9dc46ef916ca8c31ebd721cbeca7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38361 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16/mb/google/hatch/variants/helios: Remove MAX98357A devicetree entryKrishna Prasad Bhat
Helios does not have MAX98357A speaker amplifier, so remove the devicetree entry. BRANCH=firmware-hatch-12672.B Change-Id: Id02410553f018385d407086b2f9bc3ee1e7a5f40 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com>
2020-01-16soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC ↵Subrata Banik
specific Kconfig This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection into SoC specific Kconfig selection as PCH thermal device is not available with latest PCH (i.e. TGP and JSP). Also added TODO for TGL thermal configuration as applicable. TEST=Able to build and boot TGL RVP with this CL Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16drivers/spi/spi_flash: add missing status() command callbacksAaron Durbin
The adesto, amic, atmel, and stmicro spi flash drivers didn't have the status() call back. These parts do support the status command retrieval. Fill them in accordingly. Change-Id: Ie0e63bec844b8e01e292ef8c4df707494df02e69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16drivers/spi/spi_flash: separate out protection opsAaron Durbin
Put the write protection into its own object. This allows for easier future reuse of objects in future consolidation patches. It's also possible to eliminate the code implmementing these in the future if the platform doesn't require it. For now leave current behavior as-is. The names of the callbacks were shortened as they are now in the spi_flash_protection_ops object which is a new field in the spi_flash object. Change-Id: I2fec4e4430709fcf3e08a55dd36583211c035c08 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16drivers/spi/spi_flash: assume spi_flash read callback existsAaron Durbin
spi_flash_erase() and spi_flash_write() already assume their respective callbacks are supplied in the spi_flash_ops object. Make the same assumption in spi_flash_read(). In order to do this the spi_flash_ops objects from the drivers need to reference the the previously used fallback read command, spi_flash_read_chunked(). This function is made global and renamed to spi_flash_cmd_read() for consistency. By doing this further dead code elimination can be achieved when the spi flash drivers aren't included in the build. A Hatch Chrome OS build achieves a further text segment reduction of 0.5KiB in verstage, romstage, and ramstage. Change-Id: I7fee55e6ffc1983657c3adde025a0e8c9d12ca23 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-16nb/intel/sandybridge: sort LANEBASE_* defines by their addressFelix Held
Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: add macros for byte lane register offsetsFelix Held
This patch doesn't change the resulting binary of a timeless build. Change-Id: Ife0e70699df3efa162f8f6c0fd8c2928887fda2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-16nb/intel/sandybridge: refactor code around lane_base[]Felix Held
This is to get a uniform format that matches the macros added in the next patch, so that said follow-up patch won't change the output binary. lenovo/x230 still boots with this patch. Change-Id: Ibfbeb847cab09427a57bef3cbd2069036de5a21e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft resetPiotr Kleinschmidt
LDN 0xf keeps registers with open-drain configuration of the GPIO. Enabling the LDN is required for proper GPIO soft reset operation by the SuperIO driver. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15superio/nuvoton/nct5104d: Add soft reset GPIO functionalityPiotr Kleinschmidt
So far, only hard power off could reset GPIOs state to defaults: IN, Open-drain. Now, defaults are set with every boot to ensure that GPIOs are not in unknown/unwanted state. Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15soc/intel/common/block/fast_spi: don't include all spi flash driversAaron Durbin
The fast spi driver implements hardware sequencing which abstracts away the underlying spi flash commands in the hardware block. It also has its own spi flash probe function to intercept the spi flash ops. As such it's not necessary to include all spi flash drivers. On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage, romstage, and ramstage. Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15drives/spi/spi_flash: add option to not select all driversAaron Durbin
Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS, to make it easier for other parts of the code base to indicate that all spi flash drivers should not be included. Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-15soc/intel/tigerlake: Update header filesRavi Sarawadi
Modify header files to update/include tigerlake: - IOMAP BARs according to silicon reference code - Update Serial IO devices according to PCH EDS - Add board types BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I185f2c22c54a6ae386527069606abb52cce1ec80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-01-15nb/intel/sandybridge: refactor lane_registers[]Felix Held
Rename array and use defines for the values. The patch doesn't change the resulting binary when using BUILD_TIMELESS=1 Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-15nb/intel/sandybridge: drop LyCx(r, x, y) macroFelix Held
LyCx(r, x, y) was a duplicate of the CxLy(r, x, y) with different order of computation, so that the big refactoring doesn't change the output binary of a timeless build. Now this workaround can be dropped. Tested on lenovo/x230: still boots Change-Id: I251b4dd383f954b27f392190092e06a9a06668e2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-15mb/google/slippy: update VBTMatt DeVillier
The current BIOS-extracted VBT breaks backlight control with Tianocore, so replace it with one that does. Settings were exported using Intel BMP tool and the overlayed onto a GOP-format (vs BIOS format) VBT file. Test: boot google/wolf with both SeaBIOS and Tianocore payloads, verify backlight control functional under both Linux and Windows. Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-15nb/intel/sandybridge: Repurpose HOST_BRIDGE macroAngel Pons
There are more instances of PCI_DEV(0, 0, 0), so use the macro for them. Note that the resulting code with PCI_DEVFN(0, 0) is weird. It shall be replaced with config_of_soc() in a follow-up. Tested with BUILD_TIMELESS=1, resulting binary is identical. Change-Id: Ia50965a108a734d192b584291a0796a2f2bc3a55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38338 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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